Design Examples

CONTENTS

  1. 105 Examples

  2. Logic Design​​

    • Logic Circuits​

    • FSMs

Design Examples | 105 Examples of High Level and Register Transfer Level

105 Examples of High Level and Register Transfer Level Design

We used Synthagate for a lot of designs – processors, robots, controllers etc. You will find the design of 105 projects in real-time with our tool Synthagate. The designs of these 105 projects are in three zip files – you can download and play with them:

– beginning from ASMs, constructed with ASM Creator (asd files).

– beginning from ASMs in System C (cpp files).

– beginning from ASMs in VHDL (vhd files). 

You can find the detailed description of these designs in Demo 3: 105 HLS & RTL Design in 8 Minutes. The detailed transcript of Demo 3 is here

Among the projects in each set, there are six simple, seven medium, twenty large, and two huge projects. After the design, each project has 16 folders, but we left only the eight or nine more interesting folders (nine, if the project has folder Components with the predesigned IP cores).

After the design, we have 38511 files in 2126 folders. And at the beginning, we only had Algorithmic State Machines – no VHDL, no Verilog, or anything else. 

The initial parameters of projects and the results of designs from GUI.zip are summarized in table Parameters of Projects. In this table, the section Initial description contains six columns:

  • The number of operators in the project.

  • The number of microoperations in the project.

  • The number of logical conditions in the project.

  • The number of ASMs in folder Initial and its subfolder General.

  • The total number of vertices in all ASMs in the project and

  • The average number of vertices in one ASM in the project.

The next two columns in the section Description after transformation contain the information about ASMs after all transformations. The column “# levels” contains the number of the ASM transformations made by Synthagate before the design. If a project has one ASM without subASMs, the number of levels is equal to 1. If a project has several modes in folder Initial, Synthagate combines them into one ASM (plus one to the number of levels). If Synthagate minimizes the initial ASMs or ASM after combining – plus 1 to the number of levels. If a project has subASMs in folder General – we must add the number of ASM insertions, written in file Funcmi.log in folder InsertComp, to the number of levels. You can see that the minimal number of levels is one, and the maximal number of levels is ten.

The column “Vertices” in the section Description after transformation is equal to the number of vertices in ASM Funcmi.gsa in folder InsertComp after all transformations of ASMs made by Synthagate. Maybe it will be interesting for you to compare this column with the column “Vertices” in the section Initial Description.

The next two columns in the section High Level Synthesis have the number of states and the number of lines in FSM Funcmi.vhd, which is the result of the High Level Synthesis. 

The large section Register Transfer Level contains the parameters of the designs at the RTL. You can see in subsection DataPath:

  • The total number of components in Data Path.

  • The number of components instantiated in file dp.vhd.

  • The number of lines in file dp.vhd.

The next four columns contain

  • The number of states in FSM Structm.vhd (Control Unit).

  • The number of lines in FSM Structm.vhd.

  • The number of lines in the file top.vhd – the top level of RTL design.

  • The total number of lines in all files at the RTL design (in folder RTL).

The last but one column informs us about the design time of each project. And finally, in the last column, I repeated the names of the projects for ease of use with this wide table.

Synthezza logo White 2020.png

PRODUCTS

Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

Logic Synthesizer

     Overview

HLS & RTL TECHNOLOGY

Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

ASM Creator Manual

BENCHMARKS

Benchmarks of High Level Synthesis

Benchmarks of FSMs and Logic Circuits

     FSM Benchmarks

     Logic Circuits

DESIGN EXAMPLES

 

105 Designs at High Level and RTL

Logic Designs

     FSMs

     Logic Circuits

DEMO SERIES

  

COMPANY

     About Us

     Contact US

  

Copyright © 2013 - 2020 Synthezza Corporation. All Rights Reserved

Synthezza logo navy.png