Products | Logic Synthesizer | Benchmarks


These benchmarks are the result of our many years collection of examples from different sources. This section has two subsections – FSM and Logic Circuits (combinational circuits). Each subsection contains four sets according to complexity of examples – Small, Medium, Large, Huge and SuperHuge (the last only for FSMs).

Here, you can download FSM benchmarks and Logic circuit benchmarks.

Each set in subsection FSM has four folders:

To understand the ASM representation, look here.

Subsection Logic Circuits contains non-minimized multinational circuits. Each set in this subsection has five folders:

  1. ASMs (Algorithmic State Machines).

  2. T1- FSM as a table;

  3. VHDL – FSM in VHDL;

  4. Verilog – FSM in Verilog.

1. M2 – netlists in files name.m12. In this file:

  • Numbers of gates are in the first column;

  • Inputs of gates (x(i) – input of circuit, e(p) – output of gate p) are in the second column;

  • Outputs of gates are in the third column.

2. VHDL – logic circuits in VHDL;
3. Verilog – logic circuits in Verilog.

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