Products | Synthagate—HLS & RTL | Examples of High Level and RTL Design

Examples of High Level and RTL Design

We used Synthagate for a lot of designs – processors, robots, controllers etc. On our site you will find various designs for the demonstration of our HLS and RTL tool Synthagate. Each one was designed three times beginning from:​ GUI AsmCreator, ASMs in System C and ASMs in VHDL.


Several designs – Codec, ALBI, RobotBeni and four Synthagate's designs of examples from Hwang's book are described in S. Baranov's book – High Level Synthesis of Digital Systems.

Each design begins from Folder Initial which contains:

 .asd files of ASMs, if a designer begins from GUI;

.cpp files of ASMs, if a designer begins from SystemC;

.vhd files of ASMs, if a designer begins from VHDL. 


Once again, cpp and vhd files do not contain a design in System C or VHDL, but only ASMs with operators from these languages. The different representation of ASMs are here. A designer shouldn't think about minimization of initial ASMs, Synthagate will do that.

If a designer begins from ASM Creator (we strongly advise that) he must use the button build to get internal representation of ASM in three files gsa, mic and txt. If the designer prefers to use SystemC or VHDL, he should prepare ASMs as cpp or vhd files which be automatically transformed into internal files gsa, mic and txt. If the design contains generalized operators (subASMs), they must be in folder General which is a subfolder of folder Initial.


In the process of design Synthagate automatically constructs many folders corresponding to each stage of design. The design of any system contains 15 folders and each folder contains a lot of design documentation. Here we gave only five –folders Initial, Components, SpecHLS and RTL. Shorty about each folder:

  • .asd files of ASMs, if a designer begins from GUI;

  • .cpp files of ASMs, if a designer begins from SystemC;

  • .vhd files of ASMs, if a designer begins from VHDL.

Folder Spec contains two xml files - Funcmi.spec (file with functional specifications, a designer constructs it in dialog mode, and file Extspec, Synthagate constructs it automatically).

Folder HLS contains two results of High level synthesis – in VHDL (files Funcmi.vhd and my_package.vhd) and in SystemC (files funcmi.cpp and funcmi.h). Funcmi.vhd (Funcmi.cpp) presents the behavior of the whole designed system as some virtual FSM. If you have the test bench for the simulation at high level, you can use the same test bench for simulation at the RTL level in folder RTL. The designer can simulate the design with the VHDL file (funcmi.vhd) or with the System C file (funcmi.cpp).

Folder RTL, as other folders, was constructed automatically. It contains:​

  • Components of Data path in VHDL;

  • Dp.vhd– Data path in VHDL;

  • Structm.vhd– Control unit in VHDL;

  • Top.vhd– the upper level of the design as a composition of Data path and Control Unit.

File HLSTotalTime.tim contains the total time of automatic design.

We used Synthagate for a lot of designs – processors, robots, controllers etc. On our site you will find three designs using Synthagate – Codec, Nonsense and Washroom. Each one was designed three times beginning from:

  • GUI AsmCreator;

  • ASMs in System C;

  • ASMs in VHDL.

    To download the examples, please login/sign-up.

Codec demonstrates a combination of Encoder and Decoder. First, uncompressed data is writing into memory M1. Encoder reads this data from memory M1, compresses it and writes this compressed data into memory M2. Then decoder reads compressed data from memory M2, decompresses it and writes decoded data into memory M3.

To check the possibility of automatic design of very complex digital systems we gathered very different modes (operations) from various designs – robots, controllers, processors, communication devices etc. in one heap. Of course, nobody would like to implement such a wide variety of applications in one design. It is the reason we called this design Nonsense. Nevertheless, the design passes the same stages, the result of high level synthesis is in the folder HLS (file Funcmi.vhd or Funcmi.cpp), and the result of RTL design is in the folder RTL. The time of design is 32.18 seconds beginning from GUI and 37.84 seconds beginning from ASMs in System C.

Washroom is the design-joke of a virtual robot which goes to the washroom instead of us. We hope that we should never use such a robot. It is interesting that this design passes exactly through the same stages although it is a pure controller – its data path is empty.

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Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

     Examples of High Level and RTL Design

          Synthesis From GUI

          Synthesis From SystemC

          Synthesis From VHDL

Logic Synthesizer

     Logic Synthesizer Experiments



Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design






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