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Books | Four_Books (Back to Top) | Fig_56
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_package.all;
entity Funcmi is
port (
bit0 : in std_logic;
bit1 : in std_logic;
blink : out std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
hi_button : in std_logic;
idle : out std_logic;
lo_button : in std_logic;
rst : in std_logic;
s : in std_logic
);
end Funcmi;
architecture ARC_Funcmi of Funcmi is
type FSMStates is (
a1, a2, a3, a4, a5, a6, a7, a8, a9, a10
);
signal currentState : FSMStates;
signal guess : std_logic_vector(7 downto 0);
signal high : std_logic_vector(7 downto 0);
signal largest : std_logic_vector(7 downto 0);
signal low : std_logic_vector(7 downto 0);
signal sum : std_logic_vector(7 downto 0);
signal temp : std_logic_vector(7 downto 0);
signal x : std_logic_vector(7 downto 0);
signal y : std_logic_vector(7 downto 0);
begin
process (clk , rst)
procedure proc_Funcmi is
begin
case currentState is
when a1 =>
if (s and bit0 and bit1) = '1' then
sum <= x"00";
currentState <= a2;
elsif (s and bit0 and not bit1) = '1' then
largest <= x"00";
currentState <= a3;
elsif (s and not bit0 and bit1) = '1' then
low <= x"00";
high <= x"64";
blink <= '0';
currentState <= a4;
elsif (s and not bit0 and not bit1) = '1' then
x <= data_in1;
y <= data_in2;
currentState <= a5;
else
currentState <= a1;
idle <= '1';
end if;
when a2 =>
x <= data_in1;
currentState <= a6;
when a3 =>
x <= data_in;
currentState <= a7;
when a4 =>
guess <= std_logic_vector(unsigned(low) + unsigned(high));
currentState <= a8;
when a5 =>
if (x = y) then
data_out <= x;
currentState <= a1;
idle <= '1';
elsif (not (x = y) and x > y) then
x <= std_logic_vector(unsigned(x) - unsigned(y));
currentState <= a5;
else
y <= std_logic_vector(unsigned(y) - unsigned(x));
currentState <= a5;
end if;
when a6 =>
if (x = x"00") then
data_out <= sum;
currentState <= a1;
idle <= '1';
else
sum <= std_logic_vector(unsigned(sum) + unsigned(x));
currentState <= a2;
end if;
when a7 =>
data_out <= largest;
temp <= largest;
currentState <= a9;
when a8 =>
guess <= std_logic_vector(unsigned(guess) srl 1);
currentState <= a10;
when a9 =>
if (x = x"00") then
currentState <= a1;
idle <= '1';
elsif (not (x = x"00") and x > temp) then
largest <= x;
currentState <= a3;
else
x <= data_in;
currentState <= a7;
end if;
when a10 =>
if (hi_button and lo_button) = '1' then
blink <= '1';
data_out <= guess;
currentState <= a1;
idle <= '1';
elsif (hi_button and not lo_button) = '1' then
high <= guess;
currentState <= a4;
elsif (not hi_button and lo_button) = '1' then
low <= guess;
currentState <= a4;
else
currentState <= a10;
end if;
end case;
end proc_Funcmi;
begin
if (rst = '1') then
blink <= '0';
data_out <= (others => '0');
guess <= (others => '0');
high <= (others => '0');
idle <= '0';
largest <= (others => '0');
low <= (others => '0');
sum <= (others => '0');
temp <= (others => '0');
x <= (others => '0');
y <= (others => '0');
currentState <= a1;
idle <= '1';
elsif (clk'event and clk = '1') then
idle <= '0';
proc_Funcmi;
end if;
end process;
end ARC_Funcmi;
Books | Four_Books (Back to Top) | Fig_63
-- Automatically generated using Goals v1.0.1.170 04/11/2018 10:12:31
-----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.components.all;
-----------------------------
entity dp is
port
(
-- Inputs from control unit
ctr_mux1_0 : in std_logic; --(y1)
ctr_mux1_2 : in std_logic; --(y2)
x_en : in std_logic; --(y3)
ctr_mux2_2 : in std_logic; --(y4)
y_en : in std_logic; --(y5)
ctr_mux1_3 : in std_logic; --(y6)
ctr_mux2_1 : in std_logic; --(y7)
ctr_mux2_0 : in std_logic; --(y8)
blink_set : in std_logic; --(y9)
ctr_mux3 : in std_logic; --(y10)
guess_en : in std_logic; --(y11)
blink_reset : in std_logic; --(y12)
ctr_mux1_1 : in std_logic; --(y13)
high_en : in std_logic; --(y14)
low_en : in std_logic; --(y15)
temp_en : in std_logic; --(y16)
largest_en : in std_logic; --(y17)
sum_en : in std_logic; --(y18)
ctr_mux0_0 : in std_logic; --(y19)
tempreg8_1_en : in std_logic; --(y20)
ctr_mux0_1 : in std_logic; --(y21)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
-- Outputs to control unit
comp8_3_dout : out std_logic; --(x1)
comp8_4_dout : out std_logic; --(x2)
comp8_2_dout : out std_logic; --(x6)
comp8_1_dout : out std_logic; --(x7)
-- Outputs to outside
blink : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end dp;
-----------------------------------------------
architecture arc_dp of dp is
signal mux0_dout : std_logic_vector (3 downto 0);
signal mux1_dout : std_logic_vector (7 downto 0);
signal mux2_dout : std_logic_vector (7 downto 0);
signal mux3_dout : std_logic_vector (7 downto 0);
signal alu8_1_dout : std_logic_vector (7 downto 0);
signal guess_dout : std_logic_vector (7 downto 0);
signal high_dout : std_logic_vector (7 downto 0);
signal largest_dout : std_logic_vector (7 downto 0);
signal low_dout : std_logic_vector (7 downto 0);
signal sum_dout : std_logic_vector (7 downto 0);
signal temp_dout : std_logic_vector (7 downto 0);
signal tempreg8_1_dout : std_logic_vector (7 downto 0);
signal x_dout : std_logic_vector (7 downto 0);
signal y_dout : std_logic_vector (7 downto 0);
signal ctr_mux0 : std_logic_vector (1 downto 0);
signal ctr_mux1 : std_logic_vector (3 downto 0);
signal ctr_mux2 : std_logic_vector (2 downto 0);
begin
---------
-- Mux 0
---------
u1_mux0 : mux_3x4 port map ("0001", "0010", "1100", ctr_mux0, mux0_dout);
---------
-- Mux 1
---------
u2_mux1 : mux_11x8 port map (guess_dout, x_dout, sum_dout, x"00", tempreg8_1_dout, largest_dout, low_dout, y_dout, data_in1, data_in, x"64", ctr_mux1, mux1_dout);
---------
-- Mux 2
---------
u3_mux2 : mux_8x8 port map (x_dout, guess_dout, high_dout, data_in2, tempreg8_1_dout, x"00", x"01", y_dout, ctr_mux2, mux2_dout);
---------
-- Mux 3
---------
u4_mux3 : mux_2x8 port map (alu8_1_dout, tempreg8_1_dout, ctr_mux3, mux3_dout);
---------
-- blink
---------
u5_blink : rsff port map (clk, blink_reset, blink_set, rst, blink);
---------
-- guess
---------
u6_guess : reg_8bit port map (clk, rst, mux3_dout, guess_en, guess_dout);
---------
-- high
---------
u7_high : reg_8bit port map (clk, rst, mux1_dout, high_en, high_dout);
---------
-- largest
---------
u8_largest : reg_8bit port map (clk, rst, mux1_dout, largest_en, largest_dout);
---------
-- low
---------
u9_low : reg_8bit port map (clk, rst, mux2_dout, low_en, low_dout);
---------
-- sum
---------
u10_sum : reg_8bit port map (clk, rst, mux1_dout, sum_en, sum_dout);
---------
-- temp
---------
u11_temp : reg_8bit port map (clk, rst, largest_dout, temp_en, temp_dout);
---------
-- tempreg8_1
---------
u12_tempreg8_1 : reg_8bit port map (clk, rst, alu8_1_dout, tempreg8_1_en, tempreg8_1_dout);
---------
-- x
---------
u13_x : reg_8bit port map (clk, rst, mux1_dout, x_en, x_dout);
---------
-- y
---------
u14_y : reg_8bit port map (clk, rst, mux2_dout, y_en, y_dout);
---------
-- comp8_1
---------
u15_comp8_1 : g_comp generic map (comp_kind => "gr", size => 8) port map (x_dout, temp_dout, comp8_1_dout);
---------
-- comp8_2
---------
u16_comp8_2 : g_comp generic map (comp_kind => "eq", size => 8) port map (x_dout, x"00", comp8_2_dout);
---------
-- comp8_3
---------
u17_comp8_3 : g_comp generic map (comp_kind => "gr", size => 8) port map (x_dout, y_dout, comp8_3_dout);
---------
-- comp8_4
---------
u18_comp8_4 : g_comp generic map (comp_kind => "eq", size => 8) port map (x_dout, y_dout, comp8_4_dout);
---------
-- alu8_1
---------
u19_alu8_1 : alu_8bit port map (mux1_dout, mux2_dout, mux0_dout, alu8_1_dout);
-----------------------
-- Additional Signals
-----------------------
ctr_mux0 <= ctr_mux0_1 & ctr_mux0_0;
ctr_mux1 <= ctr_mux1_3 & ctr_mux1_2 & ctr_mux1_1 & ctr_mux1_0;
ctr_mux2 <= ctr_mux2_2 & ctr_mux2_1 & ctr_mux2_0;
data_out <= mux1_dout;
end arc_dp;
-----------------------------------------------
configuration cfg_dp of dp is
for arc_dp
end for;
end cfg_dp;
-----------------------------
Books | Four_Books (Back to Top) | Fig_64
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.components.all;
entity Structm is
port (
bit0 : in std_logic;
bit1 : in std_logic;
blink_reset : out std_logic;
blink_set : out std_logic;
clk : in std_logic;
comp8_1_dout : in std_logic;
comp8_2_dout : in std_logic;
comp8_3_dout : in std_logic;
comp8_4_dout : in std_logic;
ctr_mux0_0 : out std_logic;
ctr_mux0_1 : out std_logic;
ctr_mux1_0 : out std_logic;
ctr_mux1_1 : out std_logic;
ctr_mux1_2 : out std_logic;
ctr_mux1_3 : out std_logic;
ctr_mux2_0 : out std_logic;
ctr_mux2_1 : out std_logic;
ctr_mux2_2 : out std_logic;
ctr_mux3 : out std_logic;
guess_en : out std_logic;
hi_button : in std_logic;
high_en : out std_logic;
idle : out std_logic;
largest_en : out std_logic;
lo_button : in std_logic;
low_en : out std_logic;
rst : in std_logic;
s : in std_logic;
sum_en : out std_logic;
temp_en : out std_logic;
tempreg8_1_en : out std_logic;
x_en : out std_logic;
y_en : out std_logic
);
end Structm;
architecture ARC_Structm of Structm is
type FSMStates is (
a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14
);
signal currentState : FSMStates;
begin
process (clk , rst)
procedure proc_Structm is
begin
blink_reset <= '0';
blink_set <= '0';
ctr_mux0_0 <= '0';
ctr_mux0_1 <= '0';
ctr_mux1_0 <= '0';
ctr_mux1_1 <= '0';
ctr_mux1_2 <= '0';
ctr_mux1_3 <= '0';
ctr_mux2_0 <= '0';
ctr_mux2_1 <= '0';
ctr_mux2_2 <= '0';
ctr_mux3 <= '0';
guess_en <= '0';
high_en <= '0';
idle <= '0';
largest_en <= '0';
low_en <= '0';
sum_en <= '0';
temp_en <= '0';
tempreg8_1_en <= '0';
x_en <= '0';
y_en <= '0';
case currentState is
when a1 =>
if (s and bit0 and bit1) = '1' then
ctr_mux1_0 <= '1';
ctr_mux1_1 <= '1';
sum_en <= '1';
currentState <= a2;
elsif (s and bit0 and not bit1) = '1' then
ctr_mux1_0 <= '1';
ctr_mux1_1 <= '1';
largest_en <= '1';
currentState <= a3;
elsif (s and not bit0 and bit1) = '1' then
ctr_mux2_2 <= '1';
ctr_mux1_3 <= '1';
ctr_mux2_0 <= '1';
blink_reset <= '1';
ctr_mux1_1 <= '1';
high_en <= '1';
low_en <= '1';
currentState <= a4;
elsif (s and not bit0 and not bit1) = '1' then
x_en <= '1';
y_en <= '1';
ctr_mux1_3 <= '1';
ctr_mux2_1 <= '1';
ctr_mux2_0 <= '1';
currentState <= a5;
else
currentState <= a1;
idle <= '1';
end if;
when a2 =>
x_en <= '1';
ctr_mux1_3 <= '1';
currentState <= a6;
when a3 =>
ctr_mux1_0 <= '1';
x_en <= '1';
ctr_mux1_3 <= '1';
currentState <= a7;
when a4 =>
ctr_mux1_2 <= '1';
ctr_mux2_1 <= '1';
guess_en <= '1';
ctr_mux1_1 <= '1';
currentState <= a8;
when a5 =>
if (comp8_4_dout) = '1' then
ctr_mux1_0 <= '1';
currentState <= a1;
idle <= '1';
elsif (not comp8_4_dout and comp8_3_dout) = '1' then
ctr_mux1_0 <= '1';
ctr_mux2_2 <= '1';
ctr_mux2_1 <= '1';
ctr_mux2_0 <= '1';
ctr_mux0_0 <= '1';
tempreg8_1_en <= '1';
currentState <= a9;
else
ctr_mux1_0 <= '1';
ctr_mux1_2 <= '1';
ctr_mux1_1 <= '1';
ctr_mux0_0 <= '1';
tempreg8_1_en <= '1';
currentState <= a10;
end if;
when a6 =>
if (comp8_2_dout) = '1' then
ctr_mux1_1 <= '1';
currentState <= a1;
idle <= '1';
else
ctr_mux1_1 <= '1';
tempreg8_1_en <= '1';
currentState <= a11;
end if;
when a7 =>
ctr_mux1_0 <= '1';
ctr_mux1_2 <= '1';
temp_en <= '1';
currentState <= a12;
when a8 =>
ctr_mux2_2 <= '1';
ctr_mux2_1 <= '1';
tempreg8_1_en <= '1';
ctr_mux0_1 <= '1';
currentState <= a13;
when a9 =>
ctr_mux1_2 <= '1';
x_en <= '1';
currentState <= a5;
when a10 =>
ctr_mux2_2 <= '1';
y_en <= '1';
currentState <= a5;
when a11 =>
ctr_mux1_2 <= '1';
sum_en <= '1';
currentState <= a2;
when a12 =>
if (comp8_2_dout) = '1' then
currentState <= a1;
idle <= '1';
elsif (not comp8_2_dout and comp8_1_dout) = '1' then
ctr_mux1_0 <= '1';
largest_en <= '1';
currentState <= a3;
else
ctr_mux1_0 <= '1';
x_en <= '1';
ctr_mux1_3 <= '1';
currentState <= a7;
end if;
when a13 =>
ctr_mux3 <= '1';
guess_en <= '1';
currentState <= a14;
when a14 =>
if (hi_button and lo_button) = '1' then
blink_set <= '1';
currentState <= a1;
idle <= '1';
elsif (hi_button and not lo_button) = '1' then
high_en <= '1';
currentState <= a4;
elsif (not hi_button and lo_button) = '1' then
ctr_mux2_0 <= '1';
low_en <= '1';
currentState <= a4;
else
currentState <= a14;
end if;
end case;
end proc_Structm;
begin
if (rst = '1') then
blink_reset <= '0';
blink_set <= '0';
ctr_mux0_0 <= '0';
ctr_mux0_1 <= '0';
ctr_mux1_0 <= '0';
ctr_mux1_1 <= '0';
ctr_mux1_2 <= '0';
ctr_mux1_3 <= '0';
ctr_mux2_0 <= '0';
ctr_mux2_1 <= '0';
ctr_mux2_2 <= '0';
ctr_mux3 <= '0';
guess_en <= '0';
high_en <= '0';
idle <= '0';
largest_en <= '0';
low_en <= '0';
sum_en <= '0';
temp_en <= '0';
tempreg8_1_en <= '0';
x_en <= '0';
y_en <= '0';
currentState <= a1;
idle <= '1';
elsif (clk'event and clk = '0') then
idle <= '0';
proc_Structm;
end if;
end process;
end ARC_Structm;
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------
entity top is
port
(
bit0 : in std_logic;
bit1 : in std_logic;
blink : out std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
hi_button : in std_logic;
idle : out std_logic;
lo_button : in std_logic;
rst : in std_logic;
s : in std_logic
);
end top;
-----------------------------------------------
architecture arc_top of top is
component Structm is
port (
bit0 : in std_logic;
bit1 : in std_logic;
blink_reset : out std_logic;
blink_set : out std_logic;
clk : in std_logic;
comp8_1_dout : in std_logic;
comp8_2_dout : in std_logic;
comp8_3_dout : in std_logic;
comp8_4_dout : in std_logic;
ctr_mux0_0 : out std_logic;
ctr_mux0_1 : out std_logic;
ctr_mux1_0 : out std_logic;
ctr_mux1_1 : out std_logic;
ctr_mux1_2 : out std_logic;
ctr_mux1_3 : out std_logic;
ctr_mux2_0 : out std_logic;
ctr_mux2_1 : out std_logic;
ctr_mux2_2 : out std_logic;
ctr_mux3 : out std_logic;
guess_en : out std_logic;
hi_button : in std_logic;
high_en : out std_logic;
idle : out std_logic;
largest_en : out std_logic;
lo_button : in std_logic;
low_en : out std_logic;
rst : in std_logic;
s : in std_logic;
sum_en : out std_logic;
temp_en : out std_logic;
tempreg8_1_en : out std_logic;
x_en : out std_logic;
y_en : out std_logic
);
end component;
component dp is
port
(
-- Inputs from control unit
ctr_mux1_0 : in std_logic; --(y1)
ctr_mux1_2 : in std_logic; --(y2)
x_en : in std_logic; --(y3)
ctr_mux2_2 : in std_logic; --(y4)
y_en : in std_logic; --(y5)
ctr_mux1_3 : in std_logic; --(y6)
ctr_mux2_1 : in std_logic; --(y7)
ctr_mux2_0 : in std_logic; --(y8)
blink_set : in std_logic; --(y9)
ctr_mux3 : in std_logic; --(y10)
guess_en : in std_logic; --(y11)
blink_reset : in std_logic; --(y12)
ctr_mux1_1 : in std_logic; --(y13)
high_en : in std_logic; --(y14)
low_en : in std_logic; --(y15)
temp_en : in std_logic; --(y16)
largest_en : in std_logic; --(y17)
sum_en : in std_logic; --(y18)
ctr_mux0_0 : in std_logic; --(y19)
tempreg8_1_en : in std_logic; --(y20)
ctr_mux0_1 : in std_logic; --(y21)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
-- Outputs to control unit
comp8_3_dout : out std_logic; --(x1)
comp8_4_dout : out std_logic; --(x2)
comp8_2_dout : out std_logic; --(x6)
comp8_1_dout : out std_logic; --(x7)
-- Outputs to outside
blink : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
-- output of control unit
signal ctr_mux1_0 : std_logic;
signal ctr_mux1_2 : std_logic;
signal x_en : std_logic;
signal ctr_mux2_2 : std_logic;
signal y_en : std_logic;
signal ctr_mux1_3 : std_logic;
signal ctr_mux2_1 : std_logic;
signal ctr_mux2_0 : std_logic;
signal blink_set : std_logic;
signal ctr_mux3 : std_logic;
signal guess_en : std_logic;
signal blink_reset : std_logic;
signal ctr_mux1_1 : std_logic;
signal high_en : std_logic;
signal low_en : std_logic;
signal temp_en : std_logic;
signal largest_en : std_logic;
signal sum_en : std_logic;
signal ctr_mux0_0 : std_logic;
signal tempreg8_1_en : std_logic;
signal ctr_mux0_1 : std_logic;
-- output of operational unit
signal comp8_3_dout : std_logic;
signal comp8_4_dout : std_logic;
signal comp8_2_dout : std_logic;
signal comp8_1_dout : std_logic;
begin
u1_fsm : structm port map
(
bit0 => bit0 ,
bit1 => bit1 ,
blink_reset => blink_reset ,
blink_set => blink_set ,
clk => clk ,
comp8_1_dout => comp8_1_dout ,
comp8_2_dout => comp8_2_dout ,
comp8_3_dout => comp8_3_dout ,
comp8_4_dout => comp8_4_dout ,
ctr_mux0_0 => ctr_mux0_0 ,
ctr_mux0_1 => ctr_mux0_1 ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux1_1 => ctr_mux1_1 ,
ctr_mux1_2 => ctr_mux1_2 ,
ctr_mux1_3 => ctr_mux1_3 ,
ctr_mux2_0 => ctr_mux2_0 ,
ctr_mux2_1 => ctr_mux2_1 ,
ctr_mux2_2 => ctr_mux2_2 ,
ctr_mux3 => ctr_mux3 ,
guess_en => guess_en ,
hi_button => hi_button ,
high_en => high_en ,
idle => idle ,
largest_en => largest_en ,
lo_button => lo_button ,
low_en => low_en ,
rst => rst ,
s => s ,
sum_en => sum_en ,
temp_en => temp_en ,
tempreg8_1_en => tempreg8_1_en ,
x_en => x_en ,
y_en => y_en
);
u2_dp : dp port map
(
clk => clk ,
rst => rst ,
data_in => data_in ,
data_in1 => data_in1 ,
data_in2 => data_in2 ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux1_2 => ctr_mux1_2 ,
x_en => x_en ,
ctr_mux2_2 => ctr_mux2_2 ,
y_en => y_en ,
ctr_mux1_3 => ctr_mux1_3 ,
ctr_mux2_1 => ctr_mux2_1 ,
ctr_mux2_0 => ctr_mux2_0 ,
blink_set => blink_set ,
ctr_mux3 => ctr_mux3 ,
guess_en => guess_en ,
blink_reset => blink_reset ,
ctr_mux1_1 => ctr_mux1_1 ,
high_en => high_en ,
low_en => low_en ,
temp_en => temp_en ,
largest_en => largest_en ,
sum_en => sum_en ,
ctr_mux0_0 => ctr_mux0_0 ,
tempreg8_1_en => tempreg8_1_en ,
ctr_mux0_1 => ctr_mux0_1 ,
blink => blink ,
data_out => data_out ,
comp8_3_dout => comp8_3_dout ,
comp8_4_dout => comp8_4_dout ,
comp8_2_dout => comp8_2_dout ,
comp8_1_dout => comp8_1_dout
);
end arc_top;
-----------------------------------
configuration cfg_top of top is
for arc_top
end for;
end cfg_top;
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Books | Four_Books (Back to Top) | Fig_65