Design Technology | High Level Synthesis | How Does Synthagate work

How Does Synthagate Work at the High Level?

Let's look at how to design a digital system with Synthagate at the High level. As an example, we will discuss a very simple Processor. Don't spend time trying to understand how the Processor works. It is more important to understand how Synthagate works, and how it is implemented in the design of the system, which behavior is described with the set of ASMs at the High level. Just imagine that somebody has constructed ASMs of the Processor instructions and try to trace the steps of the design at the High level and the Register transfer level. You can find many examples of design here.

Figure 1. The working folder before the design

The first folder is Initial. After the "build" in ASM Creator, each ASM contains files asd, gsa, mic, and txt. Folder General is a subfolder of folder Initial. It has six subASMs of ASMs in folder Initial. (See Cpu_16_16_16Altera in 105 designs)

In our design, we have 17 ASMs in folder Initial, codes of these instructions should be in the file encoding.xml (Fig. 2). These codes will be used to combine ASMs of instructions in one combined ASM. The total number of vertices in these ASMs is 313. There are no constraints on the number of initial ASMs in the designed system.

In the Processor design, the instruction codes are predetermined. Otherwise, Synthagate will combine ASMs of modes and chooses the optimal codes, minimizing the number of vertices in the combined ASM.

If the designer would like to use some predesigned IP core, they should put it in the second folder Components. In this design, we use memory core for two memories m0 and m1 from company Altera (see file memAlt65536x16.vhd in folder Components). We had generated this file from the tool Quartus of Altera.

Figure 2. SubASMs (Generalized operator) of maincoder

Interface of Synthagate

Thus, before the design, we have asd, gsa, and txt files in folder Initial and its subfolder General and file memAlt65536x16.vhd in folder Components. Fig. 3 contains our small interface to demonstrate the Synthagate design tool.

Figure 3. Interface for design

If the designer begins from ASMs from GUI ASM Creator, they must check the box ASM in section Source, if from System C – check the box SystemC, if from VHDL – check the box VHDL. We must insert the name of the working folder d:\Synthagate\Cpu_16_16_16Altera\ in the Project Folder line of our interface. We check the box ASM (as we begin from ASMs from GUI), check the box Combine ASMs (as we have 17 instructions in this design), and check the box Include Generalized (as we have six subASMs in folder General). 

Functional specifications

To implement the High-level synthesis of the digital system, the designer does not have to define each port and signal. The special Synthagate program automatically creates an XML code of the Functional specification (file Funcmi.spec in folder Spec) and puts it in folder Spec. The designer should only insert the lengths of several ports and signals (not all, only a small part of them) into this specification in the dialog mode.


To design the Processor at the High Level and RTL, we must click Run. And immediately, Synthagate suggests that we construct Functional specifications in the dialog mode. In this design, Synthagate asked only three questions. Here we inserted the number of words in bor, m0, and m (Fig. 4).

Figure 4. Three replies in the dialog mode

After entering the memory word size m0, the special Synthagate program FuncSpecBuilder automatically creates a folder Spec and an XML code of the functional specification – file Funcmi.spec in this folder (Fig. 5). This file contains specifications of 13 ports, 11 signals, and three variables. And the program only asked us three questions.



            <port name="dma" width="1" direction="in" />

            <port name="ext_adr" width="16" direction="in" />

            <port name="ext_in" width="16" direction="out" />

            <port name="ext_out" width="16" direction="in" />

            <port name="ext_rdwr" width="1" direction="in" />

            <port name="fgi" width="1" direction="in" />

            <port name="fgi_reset" width="1" direction="out" />

            <port name="fgo" width="1" direction="in" />

            <port name="fgo_reset" width="1" direction="out" />

            <port name="inpr" width="16" direction="in" />

            <port name="m" width="1" direction="in" />

            <port name="outr" width="16" direction="out" />

            <port name="s" width="1" direction="in" />

            <signal name="bor" width="16" size="16" />

            <signal name="br" width="16" />

            <signal name="br1" width="16" />

            <signal name="ien" width="1" />

            <signal name="ir1" width="16" />

            <signal name="ir2" width="16" />

            <signal name="m0" width="16" size="65536" />

            <signal name="m1" width="16" size="65536" />

            <signal name="pc" width="16" />

            <signal name="r" width="1" />

            <signal name="zf" width="1" />

            <variable name="bor_adr" width="4" />

            <variable name="m0_address" width="16" />

            <variable name="m1_address" width="16" />




                <library name="my_package" />




Figure 5. Functional specifications Funcmi.spec

And in about 4 seconds, the design is complete – both at the High Level and the Register Transfer Level. As a result, we have 13 new folders in the working folder (Fig. 6). Each folder contains one or several stages of the design, together with the complete documentation for these stages.

Figure 6. The working folder after the design

Short design flow at the High level

Fig. 7 presents the simplified design flow of High-level synthesis. At the first step, Synthagate combines initial ASMs G1, …, GQ.  In our design, we have 17 ASMs in folder Initial, codes of these instructions are in the file encoding.xml (Fig. 2). These codes will be used to combine ASMs of instructions in one combined ASM. The total number of vertices in these ASMs is 313. There are no constraints on the number of initial ASMs in the designed system.


The combined ASM Func with 171 vertices is in files Func.gsa and Func.txt (see these files in folder Total). Synthagate has an excellent algorithm for minimization of the number of vertices in ASM – the minimized ASM Funcm.gsa with only 87 vertices is in the same folder Total. The letter m at the end of the name Funcm means that it is Func after minimization. At this stage, Synthagate checks that ASM after combining and minimization is correct (the file Funcm.chk).

Figure 7. Short design flow at the High level

Synthagate inserts SubASMs (generalized operators) into minimized ASM Funcm in folder InsertComp. ASM Funcmi (files Funcmi.gsa and Funcmi.txt) after insertion contains 109 vertices. The letter i at the end of the name Funcmi means that it is Funcm after insertion. In the file Funcmi.log, Synthagate informs which SubASMs and at what level were inserted; it also checks which the names of SubASMs correspond to their names in the main ASM Funcm. Otherwise, it gives a message about not matched names. From this file, we see that the number of levels of inclusion is equal to one. Thus, the total number of levels from Top-to-Bottom is equal to two – one for ASM combining and one for ASM inclusion. And there are no constraints on the number of generalized operators and the number of levels of such inclusions. On the site synthezza.com, you can find designs even with ten levels of inclusion.

From file Funcmi.txt, we can see that there are 43 operators (Y1 – Y43), 46 microoperations (y1 – y46), and 19 logical conditions (x1 – x19) in the design of Processor. Functional



The final step of High-Level synthesis

Synthagate begins this stage by constructing FSM Funcmi.t1 from ASM Funcmi (files Funcmi.gsa and Funcmi.txt). This FSM has 28 states, 19 inputs, 46 outputs, and 110 lines. With Functional FSM Funcmi.t1 and the functional specification Funcmi.spec (Fig. 5) as an input, Synthagate automatically constructs two designs at the same time – the first in VHDL (Funcmi.vhd) and the second in System C (Funcmi.cpp). File Funcmi.vhd is a Finite State Machine (FSM) with 28 states; its length is 638 lines. This FSM presents the whole design at the High level in VHDL. File Funcmi.cpp is a little bit longer – 773 lines with the same 28 states, and it also presents our design at the High level in System C.


After preparing a test bench, the designer can simulate the functional project with any simulation tool. The designer must choose what they would like to use in the simulation at the High level – version in VHDL or version in System C. The same testbench can be used at the last stage of design – at the RTL level.

specifications are in folder Spec – see the section Functional specifications above.

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