Design Technology | High Level Synthesis | How Does Synthagate work

How Does Synthagate Work

To demonstrate the design at High Level and RTL we provide the design process for a lossless codec, which  implements a lossless compression based on the fact, that the locally dynamic range of data is lower than the maximum dynamic range for a whole data. The encoder splits a set of data samples on segments, measures the segment's dynamic range (dynamic_range = (maximum – minimum)), subtracts minimum values from each sample of data, assigns the corresponding code of words to samples and sends them to the channel together with values of the minimum and the number of bits to represent dynamic range. The decoder receives values of the minimum and the amount of bits to represent the dynamic range of a segment, decodes a set of data samples of the segment and restores their original values by adding the minimum value to each sample of the data. 

Our goal here to show how from the several simple ASMs Synthagate designs automatically rather complex system first at the High level and then - at the Register transfer level. Thus, here we use Codec with two modes – Coder and Decoder.  In this Codec, uncompressed data is written into memory M1. Coder reads this data from M1, compresses it and writes this compressed data into memory M2. Then Decoder reads compressed data from memory M2, decompresses it and writes decoded data into memory M3.

Designer must construct two or three folders. The first one - folder Initial, which contains two modes - maincoder (Fig. 1,a) and maindecoder (Fig. 1,b). Generalized operators (subASMs) should be in folder General - the subfolder of folder Initial. Some generalized operators for Codec are drown in Fig. 2. Of course, Synthagate doesn't work with pictures. AsmCreator constructs two files – name.gsa and name.txt. 

Figure 1. ASMs maincoder (a) and maindecoder (b)

Figure 2. SubASMs (Generalized operator) of maincoder

Designer must draw ASM in ASM Creator – the special graphical interface of Synthagate. ASM Creator automatically numbers vertices, operators, microoperations and logical conditions and constructs two files – name.gsa and name.txt. Here name is the name of ASM. After that Synthagate is working not with pictures but with these files (.gsa and .txt). Fig. 3 contains file maincoder.asd with numbered verices and files maincoder.gsa (a), maincoder.mic (b), maincoder.txt (c).

Figure 3. Internal representation for maincoder

File name.gsa is the two-connected list of ASM graph. Each row of this list corresponds to one vertex. Columns in this list:

  1. The number of the vertex;

  2. The content of the vertex – Yn for operator and xm for logical condition;

  3. The number of the vertex following the operator vertex, or output ”1” of the conditional vertex;

  4. The number of the vertex following output “0” of the conditional vertex.

Vertices Begin and End are described as operator vertices.  File name.txt contains three sections - Microinstructions (operators), Microoperations and Logical conditions, presented in file name.asd. File name.mic is used when in ASM we have only numbers n, p and q for operators (Yn), microoperators (yp) and logical conditions (xm).

If a designer would like to use predesigned cores in his project, he must insert VHDL codes of these cores in the second folder "Components". In this design we used Altera's memory. Click here to look at this memory.

The third folder - Spec. To design the behavior description of digital system the designer does not have to define each port and each signal. The special Synthagate program automatically creates an XML code of Functional specifications and the designer should only insert the length of several ports and signals (not all, only a very small part of them) in this specification in the dialog mode. In file FuncmiSpec you see 38 specifications for ports, signals and variables, but only six of them were inserted in the dialog mode.

The first step of High level synthesis is ASM transformation (look at the Design flow). Synthagate combines ASMs maincoder and maindecoder (files Func.gsa and Func.txt), minimizes the combined ASM (files Funcm.gsa and Funcm.txt) and insert generalized operators (files Funcmi.gsa and Funcmi.txt).

The next step of Synthagate - High level design as a Finite state machine. Synthagate begins this stage by constructing FSM Funcmi.t1 with 77 states from ASM Funcmi.gsa.

With Functional FSM Funcmi.t1 and the functional specification Funcmi.spec (as an input, Synthagate automatically constructs two variants (in VHDL and System C) of the behavior description (design at High Level) of the whole design system – a virtual FSM in VHDL Funcmi.vhd, my_package.vhd, Funcmi.cpp and System C code for Funcmi.h.

After preparing the test bench at the behavior level the designer can simulate the functional project with any simulation tool. The same test bench can be used later on the last stage of design – after top design at the structural (RTL) level.

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Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

     Examples of High Level and RTL Design

          Synthesis From GUI

          Synthesis From SystemC

          Synthesis From VHDL

Logic Synthesizer

     Logic Synthesizer Experiments



Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design






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