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Products | Logic Synthesizer | Experiments with Logic Synthesizer

Experiments with Logic Synthesizer

In experiments with Finite state machines and combinational circuits we used examples accumulated from industry applications and students’ projects. For example, all large examples of combinational circuits were obtained from Intel.

Table 1 contains parameters of five groups of FSMs (Small, Medium, Large, Huge and Super Huge) in our experiments. The number of examples in each group is in the second column. Other columns contain the average number of states, rows in the transition table and the inputs and outputs for examples in each group.

Table 1. Parameters of FSMs

Table 2. Parameters of Combinational circuits

Tables 3 and 4 contain the results of experiments for FSMs with 4 and 6-input LUTs. There are the same names of columns in sections Area optimization and Delay optimization – average number of LUTs, Delay (average number of LUTs at the critical path) and average synthesis time in each group.

Table 3. Design FSMs (FPGA, 4-input Luts)

Table 4. Design FSMs (FPGA, 6-input Luts)

Tables 5 and 6 contain the results of experiments for Combinational circuits with 4 and 6-input LUTs. These tables have the same columns as Tables 3 – 4 for FSMs.

Table 5. Design Combinational Circuits (FPGA, 4-inputs Luts)

Table 6. Design Combinational circuits (FPGA, 6-input Luts)

Tables 7 and 8 contain the results of design FSMs and Combinational circuits with NOR – NAND gates from the library Class (Synopsys).

Table 7. Design FSMs (ASIC, library Class)

Table 8. Design Combinational circuits (ASIC, library Class)

Comparisons with other tools


In this Section we will shortly present the results of comparisons in synthesis of Finite state machines and combinational circuits between Synthagate and tools from Synopsys, Mentor Graphics and ABC tool from Berkeley. Anyone can repeat these experiments by downloading examples from our website. Not all of these experiments were carried out during the last year. We would be grateful if someone would send us new results.

Table 9 and Table 10 contains 5 columns. The name of the group (Small, Medium, Large, Huge) are in the first column. The next four columns contain the results of area optimization by Synthagate, ABC Berkelay, Precision and Quartus.

Table 9. Comparisons for FSMs (FPGA, 4-input Luts)

Table 10. Comparisons for Combinational circuits (FPGA, 4-input Luts)

Tables 11 and 12 contain the results of comparisons in design FSMs and Combinational circuits with NOR – NAND gates from the library Class (Synopsys) between Synthagate and Synopsys.

Table 11. Comparisons with Synopsys for FSMs (ASIC, library Class)

*We gave here comparisons only for six huge examples, because Synopsys couldn’t design the biggest one – Hugem.

Table 12. Comparisons for Synopsys for Combinational circuits (ASIC, library Class)