Benchmarks | Benchmarks of FSMs and Logic Circuits | Logic Circuit Benchmarks
Benchmarks of FSMs and Logic Circuits
These benchmarks are the result of our many years' collection of examples from different sources. This section has two subsections – FSM Benchmarks and Logic Circuit Benchmarks (combinational circuits). Each subsection contains four or five sets according to the complexity of examples – Small, Medium, Large, Huge, and SuperHuge (the last only for FSMs).
Each set in subsection FSM Benchmarks has four folders:
ASMs (Algorithmic State Machines).
T1 – FSM as a table;
VHDL – FSM in VHDL;
Verilog – FSM in Verilog.
To understand the ASM representation, look here
Subsection Logic Circuit Benchmarks contains non-minimized multioutput circuits. Each set in this subsection has a format M12 – netlists in files name.m12. In this file:
The numbers of gates are in the first column.
Inputs of gates (xi – input of the circuit, ep – output of gate p) are in the second column.
Outputs of gates are in the third column.