Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

     Examples of High Level and RTL Design

          Synthesis From GUI

          Synthesis From SystemC

          Synthesis From VHDL

Logic Synthesizer

     Logic Synthesizer Experiments



Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

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Products | Logic Synthesizer | Overview


Logic Synthesizer

Our fast Logic Synthesis of FSM and combinational circuits reduces the circuit area of very complex Finite state machines and combinational circuits by as much as 50%, compared with results obtained by the best industrial tools from Synopsys, Xilinx, Altera and Mentor Graphics. At the same time, Synthagate runs faster than other tools by a factor of 10 or more. Fig. 1 presents the design flow of Logic Synthesizer.

Figure 1. Logic Synthesis Design Flow