Design Technology | Algorithmic State Machines in HLS (ASMs) ASM Transformations | ASM Minimization

ASM Minimization

In this section, we will discuss minimization of conditional vertices in ASMs used in Synthagate. Fig. 1 presents nonminimal ASM Gnonmin.

Figure 1. Non-minimal ASM Gnonmin

The minimization algorithm consists of three steps. In the first step, the initial ASM is divided into such subgraphs G1, …, GQ, that for obtaining the minimal ASM it is sufficient to minimize the number of conditional vertices in each subgraph independently of one another. In the second step, for each subgraph Gq (q=1, …, Q) we must find a set of equivalent ones that contains the minimized subgraph Gq_min. At the third step, the subgraph Gq_min can be obtained by solving of the covering problem on the set of subgraphs found at the second step.

The minimized ASM Gmin constructed automatically by HLS tool Synthagate is shown in Fig. 2.

Figure 2. Minimized ASM Gmin

Synthezza High Level and RTL Design


Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

Logic Synthesizer



Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

ASM Creator Manual

Get in touch with us at


Benchmarks of High Level Synthesis

Benchmarks of FSMs and Logic Circuits

     FSM Benchmarks

     Logic Circuits



105 Designs at High Level and RTL

Logic Designs

     Logic Circuits





     About Us

     Contact US


  • YouTube
  • White Amazon Icon

Copyright © 2013 - 2020 Synthezza Corporation. All Rights Reserved

Synthezza High Level and RTL Design Logo
Synthagate HLS & RTL