SYNTHAGATE- HLS & RTL
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Products | Synthagate—HLS & RTL | Synthagate Overview
Synthagate Overview
Synthagate
Synthagate is a tool for the design of Control and Data Path Intensive Systems with very complex Control Units containing numerous inputs and outputs. Synthagate performs full automatic synthesis of digital systems from behavior specifications at the High level (HLS) and the Register Transfer Level (RTL) and allows the user to quickly implement, check and estimate multiple design versions, to find an optimized solution for the design problems, to produce the design documentation and to simplify the digital system verification problems.
The design flow in Synthagate is presented in Fig. 1. The design flow contains two large automatic stages – High Level Synthesis and Register Transfer Level.
Figure 1. Design Flow in Synthagate
Algorithmic state machines (ASMs) are used in Synthagate as an input to describe the behavior of digital systems. ASMs can be presented as:
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A graph, drawn with GUI (ASM Creator) – the special Synthagate graphical editor;
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A text in System C or VHDL.
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ASM transformations. ASM models and their transformations are used in Synthagate at all stages of behavioral (HLS) and structural (RTL) synthesis. Synthagate is the only tool that implements various transformations of initial behaviors:
ASM minimization. A designer shouldn’t think about minimization of an initial description – Synthagate automatically minimizes the number of vertices in the ASM graph.
ASM combining. If a digital system behavior is rather complex but contains several modes (instructions), Synthagate will combine them into one ASM with minimization of operator and conditional vertices. There are no constraints on the number of separate ASMs to combine.
Sub ASM insertion. At the last step of ASM transformations Synthagate inserts all component ASMs (generalized operators) and constructs one combined and minimized Functional ASM without generalized operators. This ASM presents a whole behavior of the design system. The same steps take place when a designer initially presents ASMs in System C or VHDL.
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Functional Specifications. To design the behavior description of a digital system the designer should not define each port or signal. The special Synthagate’s program FuncSpecBuilder creates an XML code of the functional specification and the designer should only insert the length of several ports and signals (not all, only a very small part of them) in the dialog mode.
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Behavior description of the design system. With Functional ASM and functional specification as an input, Synthagate automatically constructs the behavior description of the whole design system in VHDL or in System C.
After preparing the test bench at the behavior level the designer can simulate the functional project with any simulation tool. The same test bench can be used later at the last stage of design – after top design at the structural (RTL) level. For simulation at the High Level the designer can use design system in VHDL or in System C.
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ASM minimization. A designer shouldn’t think about minimization of an initial description – Synthagate automatically minimizes the number of vertices in the ASM graph.
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ASM combining. If a digital system behavior is rather complex but contains several modes (instructions), Synthagate will combine them into one ASM with minimization of operator and conditional vertices. There are no constraints on the number of separate ASMs to combine.
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Sub ASM insertion. At the last step of ASM transformations Synthagate inserts all component ASMs (generalized operators) and constructs one combined and minimized Functional ASM without generalized operators. This ASM presents a whole behavior of the design system. The same steps take place when a designer initially presents ASMs in System C or VHDL.
High Level Synthesis
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Data path design. In Data path design Synthagate uses External Specification in XML constructed automatically.
Automatic generation of components. Synthagate automatically generates VHDL codes for components of Data Path. If a designer would like to use some predesigned IP cores, he must put their RTL codes in the special folder before the High level design. Later these components will be included in the library of automatically generated units.
At the last step of Data Path design Synthagate automatically instantiates components in the Data Path.Generation VHDL code for Data Path.
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Control Unit design. Synthagate automatically creates the RTL code of the Control unit. Its input signals are feedbacks from the Data path and some input signals of the designed digital system, its outputs are micro operations implemented in the Data path and some output signals of the digital system.
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Top design. At the last stage, Synthagate creates the code for the top level automatically by instantiating Control Unit and Data Path into the top of the project.
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Automatic generation of components. Synthagate automatically generates VHDL codes for components of Data Path. If a designer would like to use some predesigned IP cores, he must put their RTL codes in the special folder before the High level design. Later these components will be included in the library of automatically generated units.
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Generation VHDL code for Data Path. At the last step of Data Path design Synthagate automatically instantiates components in the Data Path.