ALGORITHMIC STATE MACHINE (ASM) in HLS

CONTENTS

Design Technology | | ASMs in GUI, System C and VHDL

ASM in GUI, System C and VHDL

ASM (Fig. 1) is the directly connected graph containing an initial vertex (Begin), a final vertex (End) and a finite set of operator and conditional vertices. In ASM, a logical condition is written in each conditional vertex. An operator, containing zero, one, two, three or more microoperations, is written in each operator vertex of ASM. Microoperations written in one operator are implemented simultaneously.

When constructing a very complex digital system, sometimes it is very difficult (really, impossible) to describe its whole behavior by one ASM. In such a case, we can present separate sub-behaviors (modes, operations) with ASMs G1 … GQ and then combine them into one combined functional ASM G. There are no constraints on the number of such sub-behaviors. As an example, we use a design with two operations – day (Fig. 1a) and Decoder (Fig. 1b) which reads the compressed data from memory M2, decompresses it and writes decoded data into memory M3. Thus, Synthagate supports multilevel top-down behavior descriptions. A designer shouldn’t construct very complex ASMs, maybe not more than 8-10 vertices in one ASM. Fig. 1 contains two ASMs – Day (left) and Night (right) for the project Traffic Light Controller (TLC) presented without subASMs in section Figure 1. ASMs Day and Night

There are two kinds of micro operations in ASM:

• Simple micro operation, containing assignments ":=". We would like to underline here that at the behavior level (High Level Synthesis) we don’t have an architecture or Data Path of the designed system. If we write A:=B in the operator vertex, we mean that A is an input of some unit and B is the output of another unit but we don’t know yet how these units will be connected later at the Register Transfer Level (RTL) – directly or through buses (multiplexers). Here we use A and B as variables and connection between them will be constructed automatically and optimal at the design of Data path on RTL.

• Component micro operation (we call it a subASMs or generalized operator), not containing an assign operator ":=". In this disclosure they are colored by the yellow color, but the color is not important (see Fig. 1). These operators are sub ASMs and will be included in the upper ASM to get the whole behavior of digital system or one of its modes if we would like to present them separately.

Operator and micro operations:

• An operator can be either a set of micro operations, or a generalized operator.

• A generalized operator always has only one micro operation.

• The name of generalized operator must be exactly the same in all ASMs, and the same as the file name implementing that generalized operator. These names are case-insensitive – for example, MainDay and MAINDAY are the same operators.

• Microoperations (that are not generalized operators) are always assignments.

• The source and the destination of an assignment should have the same width (in bits).

• Registers/counters can be read (assigned) by bits.
For example: rg_t_int := t_int.

• Registers, counters and flip-flops cannot be read (sources) and assigned (targets) in the same operator.

• Let m is a memory and m_adr is its address. If memory has address register (m_adr), address should be assign to this register in one of the previous operators. If memory has a bus for address (without register) one of these two assignment should be in the same operator:

m_adr:=p;  m[m_adr]:=r – write the contents of register r into memory cell p; Figure 2. Generalized operators of Traffic Light Controller

Designer can draw ASMs in ASM Creator of Synthagate. After "build" (special button in ASM Creator) Synthagate immediately compiles this schematic into internal form representation used at the next steps of design.

Each generalized operator should be drawn separately. This file must have the same name as the name of generalized operator in the mother’s ASM. The generalized operator can contain generalized operators as well.  There are no constraints on the number of generalized operators and the number of levels of their inclusions. Fig. 2 presents generalized operators for ASMs day and night at Fig. 1.

If a designer wouldn’t like to use ASM Schematics (we strongly advise to use it) he can present ASMs as text files in System C (Fig. 3) or in VHDL (Fig. 4).

void day()
{
L1:
if (Start)
{
{
rg_t_int = t_int;
rg_t_sec = t_sec;
rg_t_main = t_main;
}
L2:
MainDay();
if (amb)
{
goto L4;
}
else
{
Main2Sec();
L3:
MoveSec();
if (amb)
{
L4:
AmbHandling();
if (dmain)
{
goto L3;
}
else
{
goto L2;
}
}
else
{
Sec2Main();
}
}
}
else
{
goto L1;
}

procedure day() is
begin
L1:
if (Start) then
{
rg_t_int := t_int;
rg_t_sec := t_sec;
rg_t_main := t_main;
}
L2:
MainDay();
if (amb) then
goto L4;
else
Main2Sec();
L3:
MoveSec();
if (amb) then
L4:
AmbHandling();
if (dmain) then
goto L3;
else
goto L2;
end if;
else
Sec2Main();
end if;
end if;
else
goto L1;
end if;
end day;

Figure 3. ASM Day in System C

Figure 4. ASM Day in VHDL