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Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

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     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

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ALGORITHMIC STATE MACHINE (ASM) in HLS

Design Technology | Algorithmic State Machines (ASMs) in HLS | Time in ASM

Time in ASM

To describe time in ASM let’s look at ASM in Fig. 1. Each operator can contain one, two, three etc. microoperations written in the same operator vertex. These microoperations are implemented simultaneously at the same clock.

Two sequential operators, as Y3 and Y2 in Fig. 1, are implemented at two sequential clocks. Two operators with any number of conditional vertices between them, as Y1 and Y3 are implemented at two sequential clocks.

I would like to remind you that ASM, as a Finite State Machine, is a sequential model. To describe parallel processes, we must draw several ASMs. At Fig. 2, I have shown three fragments of parallel working ASMs, dots there present some sequences of vertices. 

Figure 1. Example of ASM

The interaction between these processes is implemented by signals (microoperation). In this example, three processes begin to work simultaneously but at some time, the right one stops and waits signal y1=1 from the left process. Only then it will continue to work. In the same manner at some stage, the left process stops and waits signal y2=1 from the central one. Three processes continue to work but at some time the left and the right processes are waiting signal y3=1 from the central process etc.

Figure 2. Three pipeline processes