Products | Synthagate—HLS & RTL | What Makes Synthagate Different 

What makes Synthagate different

  1. Synthagate does not require learning a new design language. In two to three days, a designer can begin to use Synthagate to describe design system behaviors at the high level of representation.
     

  2. Synthagate is the only HLS tool to design Control Intensive and Data Path Systems with very complex Control Units containing numerous inputs and outputs. It works with hierarchical designs at the functional and structural levels.
     

  3. Synthagate is the only tool to implement various transformations of initial behavior – Algorithmic State Machines (ASMs):




    Synthagate automatically minimizes the number of vertices in initial ASMs, which reduces chip area. The designer does not need to think about the minimization of the initial behaviors.

     

  4. Synthagate uses ASMs at all stages of HLS and automatically constructs all functional and structural specifications.
     

  5. Using different generalized operators (subASMs), a designer can quickly design and check different architectures by time and/or area.
     

  6. Synthagate automatically creates direct and indirect connections (buses) between units using procedures which optimize not only the Data path (its area and speed) but also the Control unit constructed at the following design stages.
     

  7. Synthagate simplifies the verification process for the System on Chip: 

    Automatic correct-by-construction synthesis,
    Functional Verification (algorithmic level),
    Structural verification (RTL level),
    Automatic design of the skeleton of test bench for the Data path,
    Very effective synthesis of PSL assertion checkers.

  8. Synthagate provides the highest QoR, practically unlimited Capacity, record Speed of synthesis and removes most restrictions to users’ design skill sets.
     

  9. In most SoCs, a Control unit is an irregular multi-level and multi-output circuit in which delay of connectors between gates may be a lot more than a delay of gates themselves. Synthagate can construct optimized six-matrix regular FSM circuits while minimizing the area and increasing the speed. This is especially important for SoCs.
     

  10. Synthagate allows the immediate use of any IP cores designed by other companies.
     

  11. In the process of design Synthagate creates a lot of documents corresponding to each design stage. These documents can be used to prepare the project documentation. In the case of some designer’s mistakes at the initial stages of the project, these documents allow to quickly return to previous design stages and to fix all possible problems.

  • ASM minimization,

  • ASM combining,

  • ASM inclusion etc.

  • Automatic correct-by-construction synthesis,

  • Functional Verification (algorithmic level),

  • Structural verification (RTL level),

  • Automatic design of the skeleton of test bench for the Data path,

  • Very effective synthesis of PSL assertion checkers.

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PRODUCTS

Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

Logic Synthesizer

     Overview

HLS & RTL TECHNOLOGY

Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

ASM Creator Manual

BENCHMARKS

Benchmarks of High Level Synthesis

Benchmarks of FSMs and Logic Circuits

     FSM Benchmarks

     Logic Circuits

DESIGN EXAMPLES

 

105 Designs at High Level and RTL

Logic Designs

     FSMs

     Logic Circuits

DEMO SERIES

  

COMPANY

     About Us

     Contact US

  

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