Design Examples | Logic Design
Examples of Logic Design
In experiments with Finite state machines and combinational circuits, we used examples accumulated from industrial applications and student's projects. For example, all large examples of combinational circuits were obtained from Intel. You can find more details about our design in Demo 4.
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We will design FSMs from five benchmark groups, which we've collected over several years: Small, Medium, Large, Huge, and SuperHuge. You can download them here. Table 1 contains the parameters of these ASMs.
Table 1. Parameters of FSM groups
To design FSMs with Synthagte, you can begin from any of the following:
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The Algorithmic state machine presented with two files name.gsa (two connected list) and name.mic (list of operators with their microoperations).
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FSM transition table, constructed from ASM – file name.t1.
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FSM in VHDL – file name.vhd and
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FSM in Verilog – file name.v.
If you look at the bottom two rows of Table 1, you may wonder why we are designing such complicated FSMs. And I don't have a good answer for you. But ten years ago, we didn't think about many things that now seem entirely ordinary.
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Perhaps in a few years, we will want to implement some algorithms in hardware that we can now only implement in software. Or AI algorithms will be so complex that they will require very complicated FSMs to implement them. Or ask Intel why they bought Altera.
We will use the following folder structure for the design in each group:
FPGA
Area
ASMs
Verilog
Vhd
Delay
ASMs
Verilog
Vhd
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The file name_mkh.t1 contains the transition table of FSM.
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File name_mkh.t12 is the same FSM with a one-hot state assignment.
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Files name_mkh.v and name_mkh.vhd are Verilog and VHDL files constructed from FSM name_mkh.t1.
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The log file name_mkhr96_test.log tells us that No errors were found. To get such information, Synthagate makes the simulation of the constructed circuit.
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File name_mkh.m96 is the netlist of the FSM logic circuit with 6-input luts. The report is at the bottom of this file.
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File name_mkh.m97 is the same netlist as in name_mkh .m96 but with one additional second column. The number in each row in this column is equal to the number of luts in the longest path from the input to this lut. At the bottom of this netlist, we have the list of delays (in luts) for each output of the circuit and for the circuit itself.
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File name_mkh.tim contains the time of design.
We designed Finite State Machines and Logic Circuit for FPGA technology with the area and delay optimizations. Each project after the design contains the following main files:
Synthagate can design FSMs with any number of inputs in lut (up to 99). The experiments with Synthagate can help to predict technological development to determine whether it is reasonable to increase the size of the lut or not. The results of our experiments with 6-8-10-12 inputs in luts for area and delay optimizations are in Tables 2 and 3.
Table 2. Experiments with four groups of FSMs with different numbers of inputs in lut (area optimization)
Table 3. Experiments with four groups of FSMs with different numbers of inputs in lut (delay optimization)
Now let's transfer to the design of Logic (Combinational) circuits with FPGA. Table 4 contains the parameters for four groups of projects.
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We will design Logic Circuits from five benchmark groups, which we've collected over several years: Small, Medium, Large, and Huge. You can download them here. Table 1 contains the parameters of these ASMs.
Table 4. Parameters of groups of Logic circuits
For design, Synthagate implements m12 files. Such a file is a two-level netlist with And-gates and OR-gates. It is the circuit in a sum-of-products form. Its parameters are in the report at the bottom of the file.
We designed Logic Circuit for FPGA technology with the area and delay optimizations. Each project after the design contains the following main files:
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File name.m96 is the netlist of the FSM logic circuit with 6-input luts. The report is at the bottom of this file.
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File name.m97 is the same netlist as in name_mkh.m96 but with one additional second column. The number in each row in this column is equal to the number of luts in the longest path from the input to this lut. At the bottom of this netlist, we have the list of delays (in luts) for each output of the circuit and for the circuit itself.
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File name.tim contains the time of design.
Table 5 contains the comparison of designs with the area and delay optimizations.
Table 5. Area and Delay design for four groups
We haven't compared Synthagate with other design tools. However, from 2010 to 2015, comparisons for FPGA design of FSM and Logic circuits with 4-inputs luts were made at several universities. They compared Synthagate with tools of Altera, Xilinx, Mentor Graphics, and ABC from Berkeley. In all their comparisons, Synthagate was approximately 2 – 5 times better in area optimization and performed at least two times faster. Moreover, all these tools couldn't design FSMs from the groups Huge and SuperHuge. Only ABC constructed two of the smallest FSMs from the group Huge. We know of only one publication with such comparisons authored by Wegrzyn and Karatkevich**. We hope that the companies mentioned above have improved logic design within their tools in the last 5-10 years.
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However, Synthezza offers a challenge. If a company or university designs all state machines in groups Huge and SuperHuge by the end of 2020, provided that the result is within 5% of the Synthezza results, Synthezza will transfer FSM synthesis algorithms and programs to the successful party.
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NOTES: (**M. Wegrzyn and A. Karatkevich, Experimental Comparison of Synthesis ToolsAltera Quartus II and Synthagate, INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 4, PP. 357–362).