Benchmarks of HLS & RTL

Benchmarks | Benchmarks of High Level Synthesis and Register Transfer Level

Benchmarks of High level Synthesis and Register Transfer Level

The main difference between Synthagate and other design tools is that the designer doesn’t need to use hardware description languages. Instead, Synthagate uses Algorithmic State Machines (ASMs) at the different steps of the design.

The benchmarks of HLS and RTL designs are presented in three zip files for three sets of projects:

– beginning from ASMs, constructed with ASM Creator (asd files).

– beginning from ASMs in System C (cpp files).

– beginning from ASMs in VHDL (vhd files). 

In each subfolder, we have 35 projects presented in different forms (asd, cpp, and vhd) – with a total of 105. If you think that all of these projects are very simple, you are mistaken. Among the 35 projects in each set, there are six simple, seven medium, twenty large, and two huge projects. 

The designer doesn't present the design in System C or VHDL. They don't have definitions of ports, signals, or variables. When we are talking about ASMs in System C or VHDL, these ASMs are only graphs, presented with operators of System C or VHDL. We made this option in the case the designer would prefer to write them in the text file, instead of drawing ASMs. Nevertheless, we highly advise drawing ASMs in ASM Creator. 

In each benchmark, we have two or three folders – Initial, Components, and Specs. Two folders are used if the project doesn’t have predesigned IP cores. The designer should put VHDL codes of such cores in folder Components.  

Each mode (instruction) of the project is in folder Initial; their subASMs (generalized operators) are in the folder General – a subfolder of the folder Initial. In benchmarks GUI, ASM is presented by four files –asd, gsa, mic, and txt, constructed by "build" in ASM Creator. 

To implement the High-level synthesis of the digital system, the designer does not have to define each port and signal. The special Synthagate program automatically creates an XML code of the Functional specification (file Funcmi.spec in folder Spec) and puts it in folder Spec. The designer should only insert the lengths of several ports and signals (not all, only a small part of them) into this specification in the dialog mode. We had prepared Functional specifications and put them in the folder Spec of each benchmark.

You can download these benchmarks and try to design them using Synthagate or other design tools.

Synthezza High Level and RTL Design

PRODUCTS

Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

Logic Synthesizer

     Overview

HLS & RTL TECHNOLOGY

Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

ASM Creator Manual

BENCHMARKS

Benchmarks of High Level Synthesis

Benchmarks of FSMs and Logic Circuits

     FSM Benchmarks

     Logic Circuits

DESIGN EXAMPLES

 

105 Designs at High Level and RTL

Logic Designs

     Logic Circuits

     FSMs

DEMO SERIES

  

COMPANY

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