Design Technology | High Level Synthesis | How Does Synthagate work | Funcmi.spec

<external_specifications>
    <functional_specifications>
        <declarations>
            <port name="bit0" width="1" direction="in" />
            <port name="codcomplete" width="1" direction="out" />
            <port name="decodcomplete" width="1" direction="out" />
            <port name="dma" width="1" direction="in" />
            <port name="ext_adr" width="16" direction="in" />
            <port name="ext_in" width="8" direction="out" />
            <port name="ext_out" width="8" direction="in" />
            <port name="ext_rdwr" width="1" direction="in" />
            <port name="m" width="1" direction="in" />
            <port name="nelem" width="16" direction="in" />
            <port name="rwrite2m2" width="16" direction="out" />
            <port name="rwrite2m3" width="16" direction="out" />
            <port name="s" width="1" direction="in" />
            <signal name="bitcnt" width="4" />
            <signal name="br" width="8" />
            <signal name="cnt" width="8" />
            <signal name="cnt_elem" width="16" />
            <signal name="cnt_m1_m3" width="16" />
            <signal name="cnt_m2" width="16" />
            <signal name="m1" width="8" size="65536" />
            <signal name="m2" width="8" size="65536" />
            <signal name="m3" width="8" size="65536" />
            <signal name="mac1" width="16" />
            <signal name="mac2" width="16" />
            <signal name="rbyte" width="8" />
            <signal name="rd" width="8" />
            <signal name="relem" width="16" />
            <signal name="rfilelength" width="16" />
            <signal name="rlengthd" width="8" />
            <signal name="rmask" width="8" />
            <signal name="rmax" width="8" />
            <signal name="rmin" width="8" />
            <signal name="rt1" width="8" />
            <signal name="rt2" width="8" />
            <signal name="rtemp1" width="16" />
            <signal name="shcnt" width="8" />
            <variable name="m1_address" width="16" />
            <variable name="m2_address" width="16" />
            <variable name="m3_address" width="16" />
        </declarations>
        <required_libraries>
            <vhdl>
                <library name="my_package" />
            </vhdl>
        </required_libraries>
    </functional_specifications>
</external_specifications>