Design Technology | High Level Synthesis | How Does Synthagate work | Funcmi.h

#include <iostream>
#include "systemc.h"

    enum States { a1 = 1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, a47, a48, a49, a50, a51, a52, a53, a54, a55, a56, a57, a58, a59, a60, a61, a62, a63, a64, a65, a66, a67, a68, a69, a70, a71, a72, a73, a74, a75, a76, a77 };

    sc_signal< int > currentIf;
    sc_signal< sc_uint<4> > bitcnt;
    sc_signal< sc_uint<8> > br;
    sc_signal< sc_uint<8> > cnt;
    sc_signal< sc_uint<16> > cnt_elem;
    sc_signal< sc_uint<16> > cnt_m1_m3;
    sc_signal< sc_uint<16> > cnt_m2;
    sc_signal< sc_uint<8> > m1[65536];
    sc_signal< sc_uint<8> > m2[65536];
    sc_signal< sc_uint<8> > m3[65536];
    sc_signal< sc_uint<16> > mac1;
    sc_signal< sc_uint<16> > mac2;
    sc_signal< sc_uint<8> > rbyte;
    sc_signal< sc_uint<8> > rd;
    sc_signal< sc_uint<16> > relem;
    sc_signal< sc_uint<16> > rfilelength;
    sc_signal< sc_uint<8> > rlengthd;
    sc_signal< sc_uint<8> > rmask;
    sc_signal< sc_uint<8> > rmax;
    sc_signal< sc_uint<8> > rmin;
    sc_signal< sc_uint<8> > rt1;
    sc_signal< sc_uint<8> > rt2;
    sc_signal< sc_uint<16> > rtemp1;
    sc_signal< sc_uint<8> > shcnt;
    sc_in< bool > bit0;
    sc_in< bool > dma;
    sc_in< sc_uint<16> > ext_adr;
    sc_in< sc_uint<8> > ext_out;
    sc_in< bool > ext_rdwr;
    sc_in< bool > m;
    sc_in< sc_uint<16> > nelem;
    sc_in< bool > rst;
    sc_in< bool > s;
    sc_out< bool > codcomplete;
    sc_out< bool > decodcomplete;
    sc_out< sc_uint<8> > ext_in;
    sc_out< bool > idle;
    sc_out< sc_uint<16> > rwrite2m2;
    sc_out< sc_uint<16> > rwrite2m3;
    FSMStates currentState;
    sc_uint<16> m1_address;
    sc_uint<16> m2_address;
    sc_uint<16> m3_address;
    sc_in_clk clk;

    void main_proc();
    void proc_Funcmi();
        bit0                ("bit0"),
        clk                 ("clk"),
        codcomplete         ("codcomplete"),
        decodcomplete       ("decodcomplete"),
        dma                 ("dma"),
        ext_adr             ("ext_adr"),
        ext_in              ("ext_in"),
        ext_out             ("ext_out"),
        ext_rdwr            ("ext_rdwr"),
        idle                ("idle"),
        m                   ("m"),
        nelem               ("nelem"),
        rst                 ("rst"),
        rwrite2m2           ("rwrite2m2"),
        rwrite2m3           ("rwrite2m3"),
        s                   ("s")
        sensitive << clk.pos() << rst;


Synthezza logo White 2020.png


Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

     Examples of High Level and RTL Design

          Synthesis From GUI

          Synthesis From SystemC

          Synthesis From VHDL

Logic Synthesizer

     Logic Synthesizer Experiments



Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design






     About Us

     Contact US


Copyright © 2013 - 2020 Synthezza Corporation. All Rights Reserved

Synthezza logo navy.png