Books | Robot_Books | Fig_15
-- Automatically generated using Goals v1.0.0.169 28/09/2016 14:58:59
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.components.all;
-----------------------------
entity dp is
port
(
-- Inputs from control unit
distrg_en : in std_logic; --(y1)
lengctrl1_set : in std_logic; --(y2)
lengctrl2_set : in std_logic; --(y3)
rengctrl1_set : in std_logic; --(y4)
rengctrl2_set : in std_logic; --(y5)
stopflag_reset : in std_logic; --(y6)
stopflag_set : in std_logic; --(y7)
speedrg_en : in std_logic; --(y8)
ctr_mux0_1 : in std_logic; --(y9)
ctr_mux0_0 : in std_logic; --(y10)
dstrig_reset : in std_logic; --(y11)
ds_cnt_reset : in std_logic; --(y12)
dstrig_set : in std_logic; --(y13)
dstrig_cnt_reset : in std_logic; --(y14)
ds_cnt_count : in std_logic; --(y15)
dstrig_cnt_count : in std_logic; --(y16)
anglediff_en : in std_logic; --(y17)
lengctrl1_reset : in std_logic; --(y18)
lengctrl2_reset : in std_logic; --(y19)
rengctrl1_reset : in std_logic; --(y20)
rengctrl2_reset : in std_logic; --(y21)
comprg2_en : in std_logic; --(y22)
comprg1_en : in std_logic; --(y23)
pwm_reset : in std_logic; --(y24)
pwm_cnt_count : in std_logic; --(y25)
pwm_set : in std_logic; --(y26)
pwm_cnt_reset : in std_logic; --(y27)
comptrig_reset : in std_logic; --(y28)
anglecnt_reset : in std_logic; --(y29)
comptrig_set : in std_logic; --(y30)
comptrig_cnt_reset : in std_logic; --(y31)
anglecnt_count : in std_logic; --(y32)
comptrig_cnt_count : in std_logic; --(y33)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
-- Outputs to control unit
stopflag : out std_logic; --(x1)
comp20_1_dout : out std_logic; --(x3)
comp20_2_dout : out std_logic; --(x4)
comp20_3_dout : out std_logic; --(x5)
comp12_4_dout : out std_logic; --(x7)
comp20_5_dout : out std_logic; --(x8)
comp20_6_dout : out std_logic; --(x9)
comp16_7_dout : out std_logic; --(x10)
comp16_8_dout : out std_logic; --(x11)
comp12_9_dout : out std_logic; --(x13)
-- Outputs to outside
comptrig : out std_logic;
dstrig : out std_logic;
lengctrl1 : out std_logic;
lengctrl2 : out std_logic;
pwm : out std_logic;
rengctrl1 : out std_logic;
rengctrl2 : out std_logic
);
end dp;
-----------------------------------------------
architecture arc_dp of dp is
signal mux0_dout : std_logic_vector (15 downto 0);
signal alu20_1_dout : std_logic_vector (19 downto 0);
signal anglecnt_dout : std_logic_vector (19 downto 0);
signal anglediff_dout : std_logic_vector (19 downto 0);
signal comprg1_dout : std_logic_vector (19 downto 0);
signal comprg2_dout : std_logic_vector (19 downto 0);
signal comptrig_cnt_dout : std_logic_vector (11 downto 0);
signal distrg_dout : std_logic_vector (19 downto 0);
signal ds_cnt_dout : std_logic_vector (19 downto 0);
signal dstrig_cnt_dout : std_logic_vector (11 downto 0);
signal pwm_cnt_dout : std_logic_vector (15 downto 0);
signal speedrg_dout : std_logic_vector (15 downto 0);
signal ctr_mux0 : std_logic_vector (1 downto 0);
begin
---------
-- Mux 0
---------
u1_mux0 : mux_3x16 port map (x"0c35", x"186a", x"2bf2", ctr_mux0, mux0_dout);
---------
-- stopflag
---------
u2_stopflag : rsff port map (clk, stopflag_reset, stopflag_set, rst, stopflag);
---------
-- comptrig
---------
u3_comptrig : rsff port map (clk, comptrig_reset, comptrig_set, rst, comptrig);
---------
-- dstrig
---------
u4_dstrig : rsff port map (clk, dstrig_reset, dstrig_set, rst, dstrig);
---------
-- lengctrl1
---------
u5_lengctrl1 : rsff port map (clk, lengctrl1_reset, lengctrl1_set, rst, lengctrl1);
---------
-- lengctrl2
---------
u6_lengctrl2 : rsff port map (clk, lengctrl2_reset, lengctrl2_set, rst, lengctrl2);
---------
-- pwm
---------
u7_pwm : rsff port map (clk, pwm_reset, pwm_set, rst, pwm);
---------
-- rengctrl1
---------
u8_rengctrl1 : rsff port map (clk, rengctrl1_reset, rengctrl1_set, rst, rengctrl1);
---------
-- rengctrl2
---------
u9_rengctrl2 : rsff port map (clk, rengctrl2_reset, rengctrl2_set, rst, rengctrl2);
---------
-- anglediff
---------
u10_anglediff : reg_20bit port map (clk, rst, alu20_1_dout, anglediff_en, anglediff_dout);
---------
-- comprg1
---------
u11_comprg1 : reg_20bit port map (clk, rst, anglecnt_dout, comprg1_en, comprg1_dout);
---------
-- comprg2
---------
u12_comprg2 : reg_20bit port map (clk, rst, anglecnt_dout, comprg2_en, comprg2_dout);
---------
-- distrg
---------
u13_distrg : reg_20bit port map (clk, rst, ds_cnt_dout, distrg_en, distrg_dout);
---------
-- speedrg
---------
u14_speedrg : reg_16bit port map (clk, rst, mux0_dout, speedrg_en, speedrg_dout);
---------
-- anglecnt
---------
u15_anglecnt : countero_ps_20bit port map (clk, rst, anglecnt_reset, anglecnt_count, anglecnt_dout);
---------
-- comptrig_cnt
---------
u16_comptrig_cnt : countero_ps_12bit port map (clk, rst, comptrig_cnt_reset, comptrig_cnt_count, comptrig_cnt_dout);
---------
-- ds_cnt
---------
u17_ds_cnt : countero_ps_20bit port map (clk, rst, ds_cnt_reset, ds_cnt_count, ds_cnt_dout);
---------
-- dstrig_cnt
---------
u18_dstrig_cnt : countero_ps_12bit port map (clk, rst, dstrig_cnt_reset, dstrig_cnt_count, dstrig_cnt_dout);
---------
-- pwm_cnt
---------
u19_pwm_cnt : countero_ps_16bit port map (clk, rst, pwm_cnt_reset, pwm_cnt_count, pwm_cnt_dout);
---------
-- comp12_4
---------
u20_comp12_4 : g_comp generic map (comp_kind => "eq", size => 12) port map (dstrig_cnt_dout, x"1f4", comp12_4_dout);
---------
-- comp12_9
---------
u21_comp12_9 : g_comp generic map (comp_kind => "eq", size => 12) port map (comptrig_cnt_dout, x"1f4", comp12_9_dout);
---------
-- comp16_7
---------
u22_comp16_7 : g_comp generic map (comp_kind => "ls", size => 16) port map (pwm_cnt_dout, x"30d4", comp16_7_dout);
---------
-- comp16_8
---------
u23_comp16_8 : g_comp generic map (comp_kind => "ls", size => 16) port map (pwm_cnt_dout, speedrg_dout, comp16_8_dout);
---------
-- comp20_1
---------
u24_comp20_1 : g_comp generic map (comp_kind => "gr", size => 20) port map (distrg_dout, x"186a0", comp20_1_dout);
---------
-- comp20_2
---------
u25_comp20_2 : g_comp generic map (comp_kind => "gr", size => 20) port map (distrg_dout, x"3d090", comp20_2_dout);
---------
-- comp20_3
---------
u26_comp20_3 : g_comp generic map (comp_kind => "gr", size => 20) port map (distrg_dout, x"b71b0", comp20_3_dout);
---------
-- comp20_5
---------
u27_comp20_5 : g_comp generic map (comp_kind => "geq", size => 20) port map (anglediff_dout, x"00003", comp20_5_dout);
---------
-- comp20_6
---------
u28_comp20_6 : g_comp generic map (comp_kind => "ls", size => 20) port map (distrg_dout, x"186a0", comp20_6_dout);
---------
-- alu20_1
---------
u29_alu20_1 : alu_20bit port map (comprg2_dout, comprg1_dout, "0010", alu20_1_dout);
-----------------------
-- Additional Signals
-----------------------
ctr_mux0 <= ctr_mux0_1 & ctr_mux0_0;
end arc_dp;
-----------------------------------------------
configuration cfg_dp of dp is
for arc_dp
end for;
end cfg_dp;
-----------------------------