Books | Codec_Books | Fig_18
-- Automatically generated using Goals v1.0.1.170 04/11/2017 23:38:43
-----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.components.all;
-----------------------------
entity dp is
port
(
-- Inputs from control unit
codcomplete_set : in std_logic; --(y1)
rwrite2m2_en : in std_logic; --(y2)
codcomplete_reset : in std_logic; --(y3)
relem_en : in std_logic; --(y4)
decodcomplete_set : in std_logic; --(y5)
rwrite2m3_en : in std_logic; --(y6)
decodcomplete_reset : in std_logic; --(y7)
cnt_m1_m3_count : in std_logic; --(y8)
ctr_mux3_2 : in std_logic; --(y9)
ctr_mux6_1 : in std_logic; --(y10)
m1_wren : in std_logic; --(y11)
ctr_mux3_3 : in std_logic; --(y12)
ctr_mux3_1 : in std_logic; --(y13)
rfilelength_en : in std_logic; --(y14)
mac1_reset : in std_logic; --(y15)
shcnt_reset : in std_logic; --(y16)
cnt_count : in std_logic; --(y17)
ctr_mux5_2 : in std_logic; --(y18)
ctr_mux5_1 : in std_logic; --(y19)
br_en : in std_logic; --(y20)
cnt_reset : in std_logic; --(y21)
cnt_m2_reset : in std_logic; --(y22)
mac2_reset : in std_logic; --(y23)
cnt_m1_m3_en : in std_logic; --(y24)
cnt_elem_count : in std_logic; --(y25)
ctr_mux5_0 : in std_logic; --(y26)
rt2_en : in std_logic; --(y27)
cnt_elem_reset : in std_logic; --(y28)
ctr_mux5_3 : in std_logic; --(y29)
cnt_m2_count : in std_logic; --(y30)
m2_wren : in std_logic; --(y31)
mac2_count : in std_logic; --(y32)
ctr_mux4_2 : in std_logic; --(y33)
rmask_en : in std_logic; --(y34)
mac1_en : in std_logic; --(y35)
rtemp1_en : in std_logic; --(y36)
ctr_mux1_1 : in std_logic; --(y37)
ctr_mux3_0 : in std_logic; --(y38)
ctr_mux4_0 : in std_logic; --(y39)
rd_en : in std_logic; --(y40)
rmin_en : in std_logic; --(y41)
rmax_en : in std_logic; --(y42)
cnt_m1_m3_rcount : in std_logic; --(y43)
rt1_en : in std_logic; --(y44)
ctr_mux1_2 : in std_logic; --(y45)
ctr_mux2 : in std_logic; --(y46)
rbyte_en_1 : in std_logic; --(y47)
ctr_mux0_1 : in std_logic; --(y48)
rbyte_en_0 : in std_logic; --(y49)
bitcnt_count : in std_logic; --(y50)
shcnt_count : in std_logic; --(y51)
ctr_mux0_0 : in std_logic; --(y52)
ctr_mux1_0 : in std_logic; --(y53)
ctr_mux4_1 : in std_logic; --(y54)
bitcnt_reset : in std_logic; --(y55)
rlengthd_en : in std_logic; --(y56)
m3_wren : in std_logic; --(y57)
ctr_mux6_0 : in std_logic; --(y58)
mac1_count : in std_logic; --(y59)
tempreg8_1_en : in std_logic; --(y60)
tempreg16_1_en : in std_logic; --(y61)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(7 downto 0);
nelem : in std_logic_vector(15 downto 0);
-- Outputs to control unit
comp16_1_dout : out std_logic; --(x6)
comp16_2_dout : out std_logic; --(x7)
comp8_3_dout : out std_logic; --(x8)
comp8_4_dout : out std_logic; --(x9)
comp16_5_dout : out std_logic; --(x10)
comp8_6_dout : out std_logic; --(x11)
comp16_7_dout : out std_logic; --(x12)
comp8_8_dout : out std_logic; --(x13)
comp8_9_dout : out std_logic; --(x14)
comp8_10_dout : out std_logic; --(x15)
comp8_11_dout : out std_logic; --(x16)
comp4_12_dout : out std_logic; --(x17)
comp8_13_dout : out std_logic; --(x18)
comp8_14_dout : out std_logic; --(x19)
-- Outputs to outside
codcomplete : out std_logic;
decodcomplete : out std_logic;
ext_in : out std_logic_vector(7 downto 0);
rwrite2m2 : out std_logic_vector(15 downto 0);
rwrite2m3 : out std_logic_vector(15 downto 0)
);
end dp;
-----------------------------------------------
architecture arc_dp of dp is
signal mux0_dout : std_logic;
signal mux1_dout : std_logic_vector (3 downto 0);
signal mux2_dout : std_logic_vector (6 downto 0);
signal mux3_dout : std_logic_vector (7 downto 0);
signal mux4_dout : std_logic_vector (7 downto 0);
signal mux5_dout : std_logic_vector (7 downto 0);
signal mux6_dout : std_logic_vector (15 downto 0);
signal alu16_1_dout : std_logic_vector (15 downto 0);
signal alu8_1_dout : std_logic_vector (7 downto 0);
signal bitcnt_dout : std_logic_vector (3 downto 0);
signal br_dout : std_logic_vector (7 downto 0);
signal cnt_dout : std_logic_vector (7 downto 0);
signal cnt_elem_dout : std_logic_vector (15 downto 0);
signal cnt_m1_m3_dout : std_logic_vector (15 downto 0);
signal cnt_m2_dout : std_logic_vector (15 downto 0);
signal m1_q : std_logic_vector (7 downto 0);
signal m2_q : std_logic_vector (7 downto 0);
signal m3_q : std_logic_vector (7 downto 0);
signal mac1_dout : std_logic_vector (15 downto 0);
signal mac2_dout : std_logic_vector (15 downto 0);
signal rbyte_dout : std_logic_vector (7 downto 0);
signal rd_dout : std_logic_vector (7 downto 0);
signal relem_dout : std_logic_vector (15 downto 0);
signal rfilelength_dout : std_logic_vector (15 downto 0);
signal rlengthd_dout : std_logic_vector (7 downto 0);
signal rmask_dout : std_logic_vector (7 downto 0);
signal rmax_dout : std_logic_vector (7 downto 0);
signal rmin_dout : std_logic_vector (7 downto 0);
signal rt1_dout : std_logic_vector (7 downto 0);
signal rt2_dout : std_logic_vector (7 downto 0);
signal rtemp1_dout : std_logic_vector (15 downto 0);
signal shcnt_dout : std_logic_vector (7 downto 0);
signal tempreg16_1_dout : std_logic_vector (15 downto 0);
signal tempreg8_1_dout : std_logic_vector (7 downto 0);
signal ctr_mux0 : std_logic_vector (1 downto 0);
signal ctr_mux1 : std_logic_vector (2 downto 0);
signal ctr_mux3 : std_logic_vector (3 downto 0);
signal ctr_mux4 : std_logic_vector (2 downto 0);
signal ctr_mux5 : std_logic_vector (3 downto 0);
signal ctr_mux6 : std_logic_vector (1 downto 0);
signal rbyte_en : std_logic_vector (1 downto 0);
signal rbyte_din : std_logic_vector (7 downto 0);
begin
---------
-- Mux 0
---------
u1_mux0 : mux_3x1 port map ('0', '1', tempreg8_1_dout(0), ctr_mux0, mux0_dout);
---------
-- Mux 1
---------
u2_mux1 : mux_5x4 port map ("1010", "0011", "0010", "1100", "0001", ctr_mux1, mux1_dout);
---------
-- Mux 2
---------
u3_mux2 : mux_2x7 port map ("0000000", tempreg8_1_dout(7 downto 1), ctr_mux2, mux2_dout);
---------
-- Mux 3
---------
u4_mux3 : mux_10x8 port map (rbyte_dout, rmask_dout, rt2_dout, rd_dout, m3_q, cnt_dout, rt1_dout, br_dout, rmax_dout, m2_q, ctr_mux3, mux3_dout);
---------
-- Mux 4
---------
u5_mux4 : mux_5x8 port map (x"01", rmin_dout, rt2_dout, x"80", tempreg8_1_dout, ctr_mux4, mux4_dout);
---------
-- Mux 5
---------
u6_mux5 : mux_9x8 port map (m2_q, alu8_1_dout, m1_q, br_dout, tempreg8_1_dout, cnt_dout, x"ff", rmin_dout, rbyte_dout, ctr_mux5, mux5_dout);
---------
-- Mux 6
---------
u7_mux6 : mux_3x16 port map (mac2_dout, mac1_dout, ext_adr, ctr_mux6, mux6_dout);
---------
-- m1
---------
u8_m1 : mem port map (mux6_dout, clock, ext_out, m1_wren, m1_q);
---------
-- m2
---------
u9_m2 : mem port map (mux6_dout, clock, br_dout, m2_wren, m2_q);
---------
-- m3
---------
u10_m3 : mem port map (mux6_dout, clock, br_dout, m3_wren, m3_q);
---------
-- codcomplete
---------
u11_codcomplete : rsff port map (clk, codcomplete_reset, codcomplete_set, rst, codcomplete);
---------
-- decodcomplete
---------
u12_decodcomplete : rsff port map (clk, decodcomplete_reset, decodcomplete_set, rst, decodcomplete);
---------
-- rmask
---------
u13_rmask : reg_8bit port map (clk, rst, mux4_dout, rmask_en, rmask_dout);
---------
-- rmax
---------
u14_rmax : reg_8bit port map (clk, rst, br_dout, rmax_en, rmax_dout);
---------
-- rmin
---------
u15_rmin : reg_8bit port map (clk, rst, br_dout, rmin_en, rmin_dout);
---------
-- rt1
---------
u16_rt1 : reg_8bit port map (clk, rst, mux5_dout, rt1_en, rt1_dout);
---------
-- rt2
---------
u17_rt2 : reg_8bit port map (clk, rst, mux5_dout, rt2_en, rt2_dout);
---------
-- br
---------
u18_br : reg_8bit port map (clk, rst, mux5_dout, br_en, br_dout);
---------
-- rtemp1
---------
u19_rtemp1 : reg_16bit port map (clk, rst, mac1_dout, rtemp1_en, rtemp1_dout);
---------
-- rbyte
---------
u20_rbyte : reg_8bit_2en port map (clk, rst, rbyte_din, rbyte_en, rbyte_dout);
---------
-- rd
---------
u21_rd : reg_8bit port map (clk, rst, mux5_dout, rd_en, rd_dout);
---------
-- relem
---------
u22_relem : reg_16bit port map (clk, rst, nelem, relem_en, relem_dout);
---------
-- rlengthd
---------
u23_rlengthd : reg_8bit port map (clk, rst, mux3_dout, rlengthd_en, rlengthd_dout);
---------
-- rfilelength
---------
u24_rfilelength : reg_16bit port map (clk, rst, cnt_m1_m3_dout, rfilelength_en, rfilelength_dout);
---------
-- rwrite2m2
---------
u25_rwrite2m2 : reg_16bit port map (clk, rst, cnt_m2_dout, rwrite2m2_en, rwrite2m2);
---------
-- rwrite2m3
---------
u26_rwrite2m3 : reg_16bit port map (clk, rst, cnt_m1_m3_dout, rwrite2m3_en, rwrite2m3);
---------
-- tempreg16_1
---------
u27_tempreg16_1 : reg_16bit port map (clk, rst, alu16_1_dout, tempreg16_1_en, tempreg16_1_dout);
---------
-- tempreg8_1
---------
u28_tempreg8_1 : reg_8bit port map (clk, rst, alu8_1_dout, tempreg8_1_en, tempreg8_1_dout);
---------
-- mac1
---------
u29_mac1 : counter_ps_16bit port map (clk, rst, mac1_en, mac1_reset, mac1_count, rtemp1_dout, mac1_dout);
---------
-- cnt_m1_m3
---------
u30_cnt_m1_m3 : counter_pm_16bit port map (clk, rst, cnt_m1_m3_en, cnt_m1_m3_count, cnt_m1_m3_rcount, tempreg16_1_dout, cnt_m1_m3_dout);
---------
-- shcnt
---------
u31_shcnt : countero_ps_8bit port map (clk, rst, shcnt_reset, shcnt_count, shcnt_dout);
---------
-- bitcnt
---------
u32_bitcnt : countero_ps_4bit port map (clk, rst, bitcnt_reset, bitcnt_count, bitcnt_dout);
---------
-- cnt
---------
u33_cnt : countero_ps_8bit port map (clk, rst, cnt_reset, cnt_count, cnt_dout);
---------
-- cnt_m2
---------
u34_cnt_m2 : countero_ps_16bit port map (clk, rst, cnt_m2_reset, cnt_m2_count, cnt_m2_dout);
---------
-- cnt_elem
---------
u35_cnt_elem : countero_ps_16bit port map (clk, rst, cnt_elem_reset, cnt_elem_count, cnt_elem_dout);
---------
-- mac2
---------
u36_mac2 : countero_ps_16bit port map (clk, rst, mac2_reset, mac2_count, mac2_dout);
---------
-- comp4_12
---------
u37_comp4_12 : g_comp generic map (comp_kind => "eq", size => 4) port map (bitcnt_dout, x"8", comp4_12_dout);
---------
-- comp8_3
---------
u38_comp8_3 : g_comp generic map (comp_kind => "eq", size => 8) port map (cnt_dout, x"03", comp8_3_dout);
---------
-- comp8_4
---------
u39_comp8_4 : g_comp generic map (comp_kind => "eq", size => 8) port map (rlengthd_dout, x"00", comp8_4_dout);
---------
-- comp8_6
---------
u40_comp8_6 : g_comp generic map (comp_kind => "eq", size => 8) port map (br_dout, x"ff", comp8_6_dout);
---------
-- comp8_9
---------
u41_comp8_9 : g_comp generic map (comp_kind => "leq", size => 8) port map (br_dout, rmin_dout, comp8_9_dout);
---------
-- comp8_10
---------
u42_comp8_10 : g_comp generic map (comp_kind => "geq", size => 8) port map (br_dout, rmax_dout, comp8_10_dout);
---------
-- comp8_11
---------
u43_comp8_11 : g_comp generic map (comp_kind => "eq", size => 8) port map (shcnt_dout, rlengthd_dout, comp8_11_dout);
---------
-- comp8_13
---------
u44_comp8_13 : g_comp generic map (comp_kind => "eq", size => 8) port map (rt1_dout, x"00", comp8_13_dout);
---------
-- comp8_14
---------
u45_comp8_14 : g_comp generic map (comp_kind => "eq", size => 8) port map (rd_dout, x"00", comp8_14_dout);
---------
-- comp16_1
---------
u46_comp16_1 : g_comp generic map (comp_kind => "eq", size => 16) port map (cnt_m1_m3_dout, x"0000", comp16_1_dout);
---------
-- comp16_2
---------
u47_comp16_2 : g_comp generic map (comp_kind => "eq", size => 16) port map (cnt_m1_m3_dout, rfilelength_dout, comp16_2_dout);
---------
-- comp16_7
---------
u48_comp16_7 : g_comp generic map (comp_kind => "eq", size => 16) port map (cnt_elem_dout, relem_dout, comp16_7_dout);
---------
-- comp8_8
---------
u49_comp8_8 : g_comp_alu generic map (comp_kind => "eq", alu_kind => "sub", size => 8) port map (shcnt_dout, rlengthd_dout, x"01", comp8_8_dout);
---------
-- comp16_5
---------
u50_comp16_5 : g_comp_alu generic map (comp_kind => "eq", alu_kind => "sub", size => 16) port map (cnt_elem_dout, relem_dout, x"0001", comp16_5_dout);
---------
-- alu8_1
---------
u51_alu8_1 : alu_8bit port map (mux3_dout, mux4_dout, mux1_dout, alu8_1_dout);
---------
-- alu16_1
---------
u52_alu16_1 : alu_16bit port map (cnt_m1_m3_dout, relem_dout, "0010", alu16_1_dout);
-----------------------
-- Additional Signals
-----------------------
ctr_mux0 <= ctr_mux0_1 & ctr_mux0_0;
ctr_mux1 <= ctr_mux1_2 & ctr_mux1_1 & ctr_mux1_0;
ctr_mux3 <= ctr_mux3_3 & ctr_mux3_2 & ctr_mux3_1 & ctr_mux3_0;
ctr_mux4 <= ctr_mux4_2 & ctr_mux4_1 & ctr_mux4_0;
ctr_mux5 <= ctr_mux5_3 & ctr_mux5_2 & ctr_mux5_1 & ctr_mux5_0;
ctr_mux6 <= ctr_mux6_1 & ctr_mux6_0;
rbyte_din <= mux2_dout & mux0_dout;
rbyte_en <= rbyte_en_1 & rbyte_en_0;
clock <= clk;
ext_in <= mux3_dout;
end arc_dp;
-----------------------------------------------
configuration cfg_dp of dp is
for arc_dp
end for;
end cfg_dp;
-----------------------------