Design Technology | High Level Synthesis | How Does Synthagate work | Top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------
entity top is
port
(
bit0 : in std_logic;
clk : in std_logic;
codcomplete : out std_logic;
decodcomplete : out std_logic;
dma : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_in : out std_logic_vector(7 downto 0);
ext_out : in std_logic_vector(7 downto 0);
ext_rdwr : in std_logic;
idle : out std_logic;
m : in std_logic;
nelem : in std_logic_vector(15 downto 0);
rst : in std_logic;
rwrite2m2 : out std_logic_vector(15 downto 0);
rwrite2m3 : out std_logic_vector(15 downto 0);
s : in std_logic
);
end top;
-----------------------------------------------
architecture arc_top of top is
component Structm is
port (
bit0 : in std_logic;
bitcnt_count : out std_logic;
bitcnt_reset : out std_logic;
br_en : out std_logic;
clk : in std_logic;
cnt_count : out std_logic;
cnt_elem_count : out std_logic;
cnt_elem_reset : out std_logic;
cnt_m1_m3_count : out std_logic;
cnt_m1_m3_en : out std_logic;
cnt_m1_m3_rcount : out std_logic;
cnt_m2_count : out std_logic;
cnt_m2_reset : out std_logic;
cnt_reset : out std_logic;
codcomplete_reset : out std_logic;
codcomplete_set : out std_logic;
comp16_1_dout : in std_logic;
comp16_2_dout : in std_logic;
comp16_5_dout : in std_logic;
comp16_7_dout : in std_logic;
comp4_8_dout : in std_logic;
comp8_10_dout : in std_logic;
comp8_11_dout : in std_logic;
comp8_12_dout : in std_logic;
comp8_13_dout : in std_logic;
comp8_14_dout : in std_logic;
comp8_3_dout : in std_logic;
comp8_4_dout : in std_logic;
comp8_6_dout : in std_logic;
comp8_9_dout : in std_logic;
ctr_mux0_0 : out std_logic;
ctr_mux0_1 : out std_logic;
ctr_mux1_0 : out std_logic;
ctr_mux1_1 : out std_logic;
ctr_mux1_2 : out std_logic;
ctr_mux2 : out std_logic;
ctr_mux3_0 : out std_logic;
ctr_mux3_1 : out std_logic;
ctr_mux3_2 : out std_logic;
ctr_mux4_0 : out std_logic;
ctr_mux4_1 : out std_logic;
ctr_mux4_2 : out std_logic;
ctr_mux4_3 : out std_logic;
ctr_mux5_0 : out std_logic;
ctr_mux5_1 : out std_logic;
ctr_mux6_0 : out std_logic;
ctr_mux6_1 : out std_logic;
decodcomplete_reset : out std_logic;
decodcomplete_set : out std_logic;
dma : in std_logic;
ext_rdwr : in std_logic;
idle : out std_logic;
m : in std_logic;
m1_wren : out std_logic;
m2_wren : out std_logic;
m3_wren : out std_logic;
mac1_count : out std_logic;
mac1_en : out std_logic;
mac1_reset : out std_logic;
mac2_count : out std_logic;
mac2_reset : out std_logic;
rbyte_en_0 : out std_logic;
rbyte_en_1 : out std_logic;
rd_en : out std_logic;
relem_en : out std_logic;
rfilelength_en : out std_logic;
rlengthd_en : out std_logic;
rmask_en : out std_logic;
rmax_en : out std_logic;
rmin_en : out std_logic;
rst : in std_logic;
rt1_en : out std_logic;
rt2_en : out std_logic;
rtemp1_en : out std_logic;
s : in std_logic;
shcnt_count : out std_logic;
shcnt_reset : out std_logic;
tempreg16_1_en : out std_logic;
tempreg8_1_en : out std_logic
);
end component;
component dp is
port
(
-- Inputs from control unit
codcomplete_set : in std_logic; --(y1)
codcomplete_reset : in std_logic; --(y2)
relem_en : in std_logic; --(y3)
decodcomplete_set : in std_logic; --(y4)
decodcomplete_reset : in std_logic; --(y5)
cnt_m1_m3_count : in std_logic; --(y6)
ctr_mux4_3 : in std_logic; --(y7)
ctr_mux4_0 : in std_logic; --(y8)
ctr_mux6_1 : in std_logic; --(y9)
m1_wren : in std_logic; --(y10)
rfilelength_en : in std_logic; --(y11)
mac1_reset : in std_logic; --(y12)
shcnt_reset : in std_logic; --(y13)
cnt_count : in std_logic; --(y14)
ctr_mux4_1 : in std_logic; --(y15)
br_en : in std_logic; --(y16)
cnt_reset : in std_logic; --(y17)
cnt_m2_reset : in std_logic; --(y18)
mac2_reset : in std_logic; --(y19)
cnt_m1_m3_en : in std_logic; --(y20)
ctr_mux1_1 : in std_logic; --(y21)
ctr_mux3_2 : in std_logic; --(y22)
ctr_mux3_1 : in std_logic; --(y23)
ctr_mux5_0 : in std_logic; --(y24)
cnt_m1_m3_rcount : in std_logic; --(y25)
rt2_en : in std_logic; --(y26)
cnt_elem_count : in std_logic; --(y27)
rt1_en : in std_logic; --(y28)
cnt_elem_reset : in std_logic; --(y29)
cnt_m2_count : in std_logic; --(y30)
m2_wren : in std_logic; --(y31)
mac2_count : in std_logic; --(y32)
ctr_mux2 : in std_logic; --(y33)
rbyte_en_1 : in std_logic; --(y34)
ctr_mux0_1 : in std_logic; --(y35)
rbyte_en_0 : in std_logic; --(y36)
bitcnt_reset : in std_logic; --(y37)
ctr_mux4_2 : in std_logic; --(y38)
bitcnt_count : in std_logic; --(y39)
shcnt_count : in std_logic; --(y40)
ctr_mux0_0 : in std_logic; --(y41)
ctr_mux1_0 : in std_logic; --(y42)
ctr_mux3_0 : in std_logic; --(y43)
ctr_mux5_1 : in std_logic; --(y44)
rmask_en : in std_logic; --(y45)
mac1_en : in std_logic; --(y46)
mac1_count : in std_logic; --(y47)
ctr_mux6_0 : in std_logic; --(y48)
rtemp1_en : in std_logic; --(y49)
rd_en : in std_logic; --(y50)
rmin_en : in std_logic; --(y51)
rmax_en : in std_logic; --(y52)
ctr_mux1_2 : in std_logic; --(y53)
rlengthd_en : in std_logic; --(y54)
m3_wren : in std_logic; --(y55)
tempreg8_1_en : in std_logic; --(y56)
tempreg16_1_en : in std_logic; --(y57)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(7 downto 0);
nelem : in std_logic_vector(15 downto 0);
-- Outputs to control unit
comp16_1_dout : out std_logic; --(x6)
comp16_2_dout : out std_logic; --(x7)
comp8_3_dout : out std_logic; --(x8)
comp8_4_dout : out std_logic; --(x9)
comp16_5_dout : out std_logic; --(x10)
comp8_6_dout : out std_logic; --(x11)
comp16_7_dout : out std_logic; --(x12)
comp4_8_dout : out std_logic; --(x13)
comp8_9_dout : out std_logic; --(x14)
comp8_10_dout : out std_logic; --(x15)
comp8_11_dout : out std_logic; --(x16)
comp8_12_dout : out std_logic; --(x17)
comp8_13_dout : out std_logic; --(x18)
comp8_14_dout : out std_logic; --(x19)
-- Outputs to outside
codcomplete : out std_logic;
decodcomplete : out std_logic;
ext_in : out std_logic_vector(7 downto 0);
rwrite2m2 : out std_logic_vector(15 downto 0);
rwrite2m3 : out std_logic_vector(15 downto 0)
);
end component;
-- output of control unit
signal codcomplete_set : std_logic;
signal codcomplete_reset : std_logic;
signal relem_en : std_logic;
signal decodcomplete_set : std_logic;
signal decodcomplete_reset : std_logic;
signal cnt_m1_m3_count : std_logic;
signal ctr_mux4_3 : std_logic;
signal ctr_mux4_0 : std_logic;
signal ctr_mux6_1 : std_logic;
signal m1_wren : std_logic;
signal rfilelength_en : std_logic;
signal mac1_reset : std_logic;
signal shcnt_reset : std_logic;
signal cnt_count : std_logic;
signal ctr_mux4_1 : std_logic;
signal br_en : std_logic;
signal cnt_reset : std_logic;
signal cnt_m2_reset : std_logic;
signal mac2_reset : std_logic;
signal cnt_m1_m3_en : std_logic;
signal ctr_mux1_1 : std_logic;
signal ctr_mux3_2 : std_logic;
signal ctr_mux3_1 : std_logic;
signal ctr_mux5_0 : std_logic;
signal cnt_m1_m3_rcount : std_logic;
signal rt2_en : std_logic;
signal cnt_elem_count : std_logic;
signal rt1_en : std_logic;
signal cnt_elem_reset : std_logic;
signal cnt_m2_count : std_logic;
signal m2_wren : std_logic;
signal mac2_count : std_logic;
signal ctr_mux2 : std_logic;
signal rbyte_en_1 : std_logic;
signal ctr_mux0_1 : std_logic;
signal rbyte_en_0 : std_logic;
signal bitcnt_reset : std_logic;
signal ctr_mux4_2 : std_logic;
signal bitcnt_count : std_logic;
signal shcnt_count : std_logic;
signal ctr_mux0_0 : std_logic;
signal ctr_mux1_0 : std_logic;
signal ctr_mux3_0 : std_logic;
signal ctr_mux5_1 : std_logic;
signal rmask_en : std_logic;
signal mac1_en : std_logic;
signal mac1_count : std_logic;
signal ctr_mux6_0 : std_logic;
signal rtemp1_en : std_logic;
signal rd_en : std_logic;
signal rmin_en : std_logic;
signal rmax_en : std_logic;
signal ctr_mux1_2 : std_logic;
signal rlengthd_en : std_logic;
signal m3_wren : std_logic;
signal tempreg8_1_en : std_logic;
signal tempreg16_1_en : std_logic;
-- output of operational unit
signal comp16_1_dout : std_logic;
signal comp16_2_dout : std_logic;
signal comp8_3_dout : std_logic;
signal comp8_4_dout : std_logic;
signal comp16_5_dout : std_logic;
signal comp8_6_dout : std_logic;
signal comp16_7_dout : std_logic;
signal comp4_8_dout : std_logic;
signal comp8_9_dout : std_logic;
signal comp8_10_dout : std_logic;
signal comp8_11_dout : std_logic;
signal comp8_12_dout : std_logic;
signal comp8_13_dout : std_logic;
signal comp8_14_dout : std_logic;
begin
u1_fsm : structm port map
(
bit0 => bit0 ,
bitcnt_count => bitcnt_count ,
bitcnt_reset => bitcnt_reset ,
br_en => br_en ,
clk => clk ,
cnt_count => cnt_count ,
cnt_elem_count => cnt_elem_count ,
cnt_elem_reset => cnt_elem_reset ,
cnt_m1_m3_count => cnt_m1_m3_count ,
cnt_m1_m3_en => cnt_m1_m3_en ,
cnt_m1_m3_rcount => cnt_m1_m3_rcount ,
cnt_m2_count => cnt_m2_count ,
cnt_m2_reset => cnt_m2_reset ,
cnt_reset => cnt_reset ,
codcomplete_reset => codcomplete_reset ,
codcomplete_set => codcomplete_set ,
comp16_1_dout => comp16_1_dout ,
comp16_2_dout => comp16_2_dout ,
comp16_5_dout => comp16_5_dout ,
comp16_7_dout => comp16_7_dout ,
comp4_8_dout => comp4_8_dout ,
comp8_10_dout => comp8_10_dout ,
comp8_11_dout => comp8_11_dout ,
comp8_12_dout => comp8_12_dout ,
comp8_13_dout => comp8_13_dout ,
comp8_14_dout => comp8_14_dout ,
comp8_3_dout => comp8_3_dout ,
comp8_4_dout => comp8_4_dout ,
comp8_6_dout => comp8_6_dout ,
comp8_9_dout => comp8_9_dout ,
ctr_mux0_0 => ctr_mux0_0 ,
ctr_mux0_1 => ctr_mux0_1 ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux1_1 => ctr_mux1_1 ,
ctr_mux1_2 => ctr_mux1_2 ,
ctr_mux2 => ctr_mux2 ,
ctr_mux3_0 => ctr_mux3_0 ,
ctr_mux3_1 => ctr_mux3_1 ,
ctr_mux3_2 => ctr_mux3_2 ,
ctr_mux4_0 => ctr_mux4_0 ,
ctr_mux4_1 => ctr_mux4_1 ,
ctr_mux4_2 => ctr_mux4_2 ,
ctr_mux4_3 => ctr_mux4_3 ,
ctr_mux5_0 => ctr_mux5_0 ,
ctr_mux5_1 => ctr_mux5_1 ,
ctr_mux6_0 => ctr_mux6_0 ,
ctr_mux6_1 => ctr_mux6_1 ,
decodcomplete_reset => decodcomplete_reset ,
decodcomplete_set => decodcomplete_set ,
dma => dma ,
ext_rdwr => ext_rdwr ,
idle => idle ,
m => m ,
m1_wren => m1_wren ,
m2_wren => m2_wren ,
m3_wren => m3_wren ,
mac1_count => mac1_count ,
mac1_en => mac1_en ,
mac1_reset => mac1_reset ,
mac2_count => mac2_count ,
mac2_reset => mac2_reset ,
rbyte_en_0 => rbyte_en_0 ,
rbyte_en_1 => rbyte_en_1 ,
rd_en => rd_en ,
relem_en => relem_en ,
rfilelength_en => rfilelength_en ,
rlengthd_en => rlengthd_en ,
rmask_en => rmask_en ,
rmax_en => rmax_en ,
rmin_en => rmin_en ,
rst => rst ,
rt1_en => rt1_en ,
rt2_en => rt2_en ,
rtemp1_en => rtemp1_en ,
s => s ,
shcnt_count => shcnt_count ,
shcnt_reset => shcnt_reset ,
tempreg16_1_en => tempreg16_1_en ,
tempreg8_1_en => tempreg8_1_en
);
u2_dp : dp port map
(
clk => clk ,
rst => rst ,
ext_adr => ext_adr ,
ext_out => ext_out ,
nelem => nelem ,
codcomplete_set => codcomplete_set ,
codcomplete_reset => codcomplete_reset ,
relem_en => relem_en ,
decodcomplete_set => decodcomplete_set ,
decodcomplete_reset => decodcomplete_reset ,
cnt_m1_m3_count => cnt_m1_m3_count ,
ctr_mux4_3 => ctr_mux4_3 ,
ctr_mux4_0 => ctr_mux4_0 ,
ctr_mux6_1 => ctr_mux6_1 ,
m1_wren => m1_wren ,
rfilelength_en => rfilelength_en ,
mac1_reset => mac1_reset ,
shcnt_reset => shcnt_reset ,
cnt_count => cnt_count ,
ctr_mux4_1 => ctr_mux4_1 ,
br_en => br_en ,
cnt_reset => cnt_reset ,
cnt_m2_reset => cnt_m2_reset ,
mac2_reset => mac2_reset ,
cnt_m1_m3_en => cnt_m1_m3_en ,
ctr_mux1_1 => ctr_mux1_1 ,
ctr_mux3_2 => ctr_mux3_2 ,
ctr_mux3_1 => ctr_mux3_1 ,
ctr_mux5_0 => ctr_mux5_0 ,
cnt_m1_m3_rcount => cnt_m1_m3_rcount ,
rt2_en => rt2_en ,
cnt_elem_count => cnt_elem_count ,
rt1_en => rt1_en ,
cnt_elem_reset => cnt_elem_reset ,
cnt_m2_count => cnt_m2_count ,
m2_wren => m2_wren ,
mac2_count => mac2_count ,
ctr_mux2 => ctr_mux2 ,
rbyte_en_1 => rbyte_en_1 ,
ctr_mux0_1 => ctr_mux0_1 ,
rbyte_en_0 => rbyte_en_0 ,
bitcnt_reset => bitcnt_reset ,
ctr_mux4_2 => ctr_mux4_2 ,
bitcnt_count => bitcnt_count ,
shcnt_count => shcnt_count ,
ctr_mux0_0 => ctr_mux0_0 ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux3_0 => ctr_mux3_0 ,
ctr_mux5_1 => ctr_mux5_1 ,
rmask_en => rmask_en ,
mac1_en => mac1_en ,
mac1_count => mac1_count ,
ctr_mux6_0 => ctr_mux6_0 ,
rtemp1_en => rtemp1_en ,
rd_en => rd_en ,
rmin_en => rmin_en ,
rmax_en => rmax_en ,
ctr_mux1_2 => ctr_mux1_2 ,
rlengthd_en => rlengthd_en ,
m3_wren => m3_wren ,
tempreg8_1_en => tempreg8_1_en ,
tempreg16_1_en => tempreg16_1_en ,
codcomplete => codcomplete ,
decodcomplete => decodcomplete ,
ext_in => ext_in ,
rwrite2m2 => rwrite2m2 ,
rwrite2m3 => rwrite2m3 ,
comp16_1_dout => comp16_1_dout ,
comp16_2_dout => comp16_2_dout ,
comp8_3_dout => comp8_3_dout ,
comp8_4_dout => comp8_4_dout ,
comp16_5_dout => comp16_5_dout ,
comp8_6_dout => comp8_6_dout ,
comp16_7_dout => comp16_7_dout ,
comp4_8_dout => comp4_8_dout ,
comp8_9_dout => comp8_9_dout ,
comp8_10_dout => comp8_10_dout ,
comp8_11_dout => comp8_11_dout ,
comp8_12_dout => comp8_12_dout ,
comp8_13_dout => comp8_13_dout ,
comp8_14_dout => comp8_14_dout
);
end arc_top;
-----------------------------------
configuration cfg_top of top is
for arc_top
end for;
end cfg_top;
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