ALBI BOOKS
Menu |
Books | ALBI_Books (Back to Top) | Fig_23
-- Automatically generated using Goals v1.0.0.169 20/10/2016 12:16:36
-----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.components.all;
-----------------------------
entity dp is
port
(
-- Inputs from control unit
ctr_mux2_0 : in std_logic; --(y1)
br_en : in std_logic; --(y2)
ctr_mux1_0 : in std_logic; --(y3)
ctr_mux0 : in std_logic; --(y4)
ir2_en : in std_logic; --(y5)
ctr_mux1_2 : in std_logic; --(y6)
bor_en : in std_logic; --(y7)
ralu_en : in std_logic; --(y8)
ctr_mux2_1 : in std_logic; --(y9)
pc_en : in std_logic; --(y10)
inpr_en : in std_logic; --(y11)
ctr_mux1_1 : in std_logic; --(y12)
m1_rdwr : in std_logic; --(y13)
m0_rdwr : in std_logic; --(y14)
ctr_mux2_2 : in std_logic; --(y15)
rialu_en : in std_logic; --(y16)
pc_count : in std_logic; --(y17)
ir1_en : in std_logic; --(y18)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
-- Outputs to control unit
ir1_9 : out std_logic; --(x1)
ir1_10 : out std_logic; --(x2)
ir1_8 : out std_logic; --(x3)
comp4_1_dout : out std_logic; --(x10)
-- Outputs to outside
ext_in : out std_logic_vector(15 downto 0)
);
end dp;
-----------------------------------------------
architecture arc_dp of dp is
signal mux1_dout : std_logic_vector (15 downto 0);
signal mux2_dout : std_logic_vector (15 downto 0);
signal mux0_dout : std_logic_vector (3 downto 0);
signal alu_alu : std_logic_vector (15 downto 0);
signal bor_dout : std_logic_vector (15 downto 0);
signal br_dout : std_logic_vector (15 downto 0);
signal ialu_ialu : std_logic_vector (15 downto 0);
signal inpr_dout : std_logic_vector (15 downto 0);
signal ir1_dout : std_logic_vector (15 downto 0);
signal ir2_dout : std_logic_vector (15 downto 0);
signal m0_dout : std_logic_vector (15 downto 0);
signal m1_dout : std_logic_vector (15 downto 0);
signal pc_dout : std_logic_vector (15 downto 0);
signal ralu_dout : std_logic_vector (15 downto 0);
signal rialu_dout : std_logic_vector (15 downto 0);
signal ctr_mux1 : std_logic_vector (2 downto 0);
signal ctr_mux2 : std_logic_vector (2 downto 0);
begin
---------
-- Mux 1
---------
u1_mux1 : mux_6x16 port map (ext_adr, ir2_dout, pc_dout, inpr_dout, br_dout, ralu_dout, ctr_mux1, mux1_dout);
---------
-- Mux 2
---------
u2_mux2 : mux_6x16 port map (bor_dout, m1_dout, ir2_dout, br_dout, m0_dout, rialu_dout, ctr_mux2, mux2_dout);
---------
-- Mux 0
---------
u3_mux0 : mux_2x4 port map (ir1_dout(3 downto 0), ir1_dout(7 downto 4), ctr_mux0, mux0_dout);
---------
-- ALU
---------
u4_alu : alub port map (br_dout, ir2_dout, ir1_dout(15 downto 11), alu_alu);
---------
-- IALU
---------
u5_ialu : ialub port map (ir2_dout, br_dout, ialu_ialu);
---------
-- ir2
---------
u6_ir2 : reg_16bit port map (clk, rst, mux2_dout, ir2_en, ir2_dout);
---------
-- br
---------
u7_br : reg_16bit port map (clk, rst, mux2_dout, br_en, br_dout);
---------
-- ir1
---------
u8_ir1 : reg_16bit port map (clk, rst, m0_dout, ir1_en, ir1_dout);
---------
-- rialu
---------
u9_rialu : reg_16bit port map (clk, rst, ialu_ialu, rialu_en, rialu_dout);
---------
-- ralu
---------
u10_ralu : reg_16bit port map (clk, rst, alu_alu, ralu_en, ralu_dout);
---------
-- inpr
---------
u11_inpr : reg_16bit port map (clk, rst, data_in, inpr_en, inpr_dout);
---------
-- bor
---------
u12_bor : bor_4adr_16bit port map (clk, rst, mux0_dout, mux1_dout, bor_en, bor_dout);
---------
-- m0
---------
u13_m0 : ram_16adr_16bit port map (clk, mux1_dout, ext_out, m0_rdwr, m0_dout);
---------
-- m1
---------
u14_m1 : ram_16adr_16bit port map (clk, mux1_dout, ext_out, m1_rdwr, m1_dout);
---------
-- pc
---------
u15_pc : counter_p_16bit port map (clk, rst, pc_en, pc_count, mux2_dout, pc_dout);
---------
-- comp4_1
---------
u16_comp4_1 : g_comp generic map (comp_kind => "eq", size => 4) port map (ir1_dout(3 downto 0), "0000", comp4_1_dout);
-----------------------
-- Additional Signals
-----------------------
ctr_mux1 <= ctr_mux1_2 & ctr_mux1_1 & ctr_mux1_0;
ctr_mux2 <= ctr_mux2_2 & ctr_mux2_1 & ctr_mux2_0;
ext_in <= mux2_dout;
ir1_9 <= ir1_dout(9);
ir1_10 <= ir1_dout(10);
ir1_8 <= ir1_dout(8);
end arc_dp;
-----------------------------------------------
configuration cfg_dp of dp is
for arc_dp
end for;
end cfg_dp;
-----------------------------
Fig_23
Fig_31
Fig_32
Fig_33
Fig_34
Fig_031
Fig_034
ALBI.ZIP
Books | ALBI_Books (Back to Top) | Fig_31
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_package.all;
entity Funcmi is
port (
bit0 : in std_logic;
bit1 : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dma : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_in : out std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(15 downto 0);
ext_rdwr : in std_logic;
idle : out std_logic;
m : in std_logic;
rst : in std_logic;
s : in std_logic
);
end Funcmi;
architecture ARC_Funcmi of Funcmi is
type FSMStates is (
a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15,
a16, a17, a18
);
type bor_type is array (integer range 0 to 15) of std_logic_vector(15 downto 0);
type m0_type is array (integer range 0 to 65535) of std_logic_vector(15 downto 0);
type m1_type is array (integer range 0 to 65535) of std_logic_vector(15 downto 0);
signal bor : bor_type;
signal br : std_logic_vector(15 downto 0);
signal currentState : FSMStates;
signal inpr : std_logic_vector(15 downto 0);
signal ir1 : std_logic_vector(15 downto 0);
signal ir2 : std_logic_vector(15 downto 0);
signal m0 : m0_type;
signal m1 : m1_type;
signal pc : std_logic_vector(15 downto 0);
signal ralu : std_logic_vector(15 downto 0);
signal rialu : std_logic_vector(15 downto 0);
begin
process (clk , rst)
variable alu : std_logic_vector(15 downto 0);
variable alu_ctr : std_logic_vector(4 downto 0);
variable alu_in1 : std_logic_vector(15 downto 0);
variable alu_in2 : std_logic_vector(15 downto 0);
variable bor_adr : std_logic_vector(3 downto 0);
variable ialu : std_logic_vector(15 downto 0);
variable ialu_in1 : std_logic_vector(15 downto 0);
variable ialu_in2 : std_logic_vector(15 downto 0);
variable m0_adr : std_logic_vector(15 downto 0);
variable m1_adr : std_logic_vector(15 downto 0);
procedure proc_Funcmi is
begin
case currentState is
when a1 =>
if (s and dma and ext_rdwr and m) = '1' then
m1_adr := ext_adr;
m1(to_integer(unsigned(m1_adr))) <= ext_out;
currentState <= a1;
idle <= '1';
elsif (s and dma and ext_rdwr and not m) = '1' then
m0_adr := ext_adr;
m0(to_integer(unsigned(m0_adr))) <= ext_out;
currentState <= a1;
idle <= '1';
elsif (s and dma and not ext_rdwr and m) = '1' then
m1_adr := ext_adr;
ext_in <= m1(to_integer(unsigned(m1_adr)));
currentState <= a1;
idle <= '1';
elsif (s and dma and not ext_rdwr and not m) = '1' then
m0_adr := ext_adr;
ext_in <= m0(to_integer(unsigned(m0_adr)));
currentState <= a1;
idle <= '1';
elsif (s and not dma) = '1' then
m0_adr := pc;
ir1 <= m0(to_integer(unsigned(m0_adr)));
currentState <= a8;
else
currentState <= a1;
idle <= '1';
end if;
when a2 =>
if (bit1) = '1' then
bor_adr := ir1(7 downto 4);
bor(to_integer(unsigned(bor_adr))) <= br;
currentState <= a1;
idle <= '1';
else
ir2 <= br;
currentState <= a6;
end if;
when a3 =>
alu_in1 := br;
alu_in2 := ir2;
alu_ctr := ir1(15 downto 11);
alub(alu_in1, alu_in2, alu_ctr, alu);
ralu <= alu;
currentState <= a5;
when a4 =>
if (ir1(9)) = '1' then
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a2;
else
bor_adr := ir1(7 downto 4);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a3;
end if;
when a5 =>
bor_adr := ir1(7 downto 4);
bor(to_integer(unsigned(bor_adr))) <= ralu;
currentState <= a1;
idle <= '1';
when a6 =>
if (bit1) = '1' then
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a2;
else
bor_adr := ir1(7 downto 4);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a3;
end if;
when a7 =>
pc <= std_logic_vector(unsigned(pc) + 1);
currentState <= a17;
when a8 =>
pc <= std_logic_vector(unsigned(pc) + 1);
currentState <= a18;
when a9 =>
bor_adr := ir1(7 downto 4);
bor(to_integer(unsigned(bor_adr))) <= inpr;
currentState <= a1;
idle <= '1';
when a10 =>
if (ir1(9)) = '1' then
ir2 <= br;
currentState <= a6;
else
bor_adr := ir1(7 downto 4);
bor(to_integer(unsigned(bor_adr))) <= br;
currentState <= a1;
idle <= '1';
end if;
when a11 =>
bor_adr := ir1(7 downto 4);
bor(to_integer(unsigned(bor_adr))) <= br;
currentState <= a1;
idle <= '1';
when a12 =>
ialu_in1 := ir2;
ialu_in2 := br;
ialub(ialu_in1, ialu_in2, ialu);
rialu <= ialu;
currentState <= a15;
when a13 =>
ir2 <= br;
currentState <= a16;
when a14 =>
if (bit0) = '1' then
m1_adr := ir2;
pc <= m1(to_integer(unsigned(m1_adr)));
currentState <= a1;
idle <= '1';
else
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a2;
end if;
when a15 =>
ir2 <= rialu;
currentState <= a14;
when a16 =>
if (ir1(3 downto 0) = "0000" and (bit0) = '1') then
m1_adr := ir2;
pc <= m1(to_integer(unsigned(m1_adr)));
currentState <= a1;
idle <= '1';
elsif (ir1(3 downto 0) = "0000" and (not bit0) = '1') then
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a2;
else
bor_adr := ir1(3 downto 0);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a12;
end if;
when a17 =>
if (ir1(8) and bit0) = '1' then
pc <= ir2;
currentState <= a1;
idle <= '1';
elsif (ir1(8) and not bit0 and bit1) = '1' then
br <= ir2;
currentState <= a11;
elsif (ir1(8) and not bit0 and not bit1) = '1' then
bor_adr := ir1(7 downto 4);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a3;
elsif (not ir1(8) and ir1(9)) = '1' then
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a13;
elsif (ir1(3 downto 0) = "0000" and (not ir1(8) and not ir1(9) and bit0) = '1') then
m1_adr := ir2;
pc <= m1(to_integer(unsigned(m1_adr)));
currentState <= a1;
idle <= '1';
elsif (ir1(3 downto 0) = "0000" and (not ir1(8) and not ir1(9) and not bit0) = '1') then
m1_adr := ir2;
br <= m1(to_integer(unsigned(m1_adr)));
currentState <= a2;
else
bor_adr := ir1(3 downto 0);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a12;
end if;
when a18 =>
if (bit0 and bit1) = '1' then
inpr <= data_in;
currentState <= a9;
elsif (bit0 and not bit1 and ir1(10)) = '1' then
m0_adr := pc;
ir2 <= m0(to_integer(unsigned(m0_adr)));
currentState <= a7;
elsif (bit0 and not bit1 and not ir1(10)) = '1' then
bor_adr := ir1(3 downto 0);
pc <= bor(to_integer(unsigned(bor_adr)));
currentState <= a1;
idle <= '1';
elsif (not bit0 and ir1(10)) = '1' then
m0_adr := pc;
ir2 <= m0(to_integer(unsigned(m0_adr)));
currentState <= a7;
elsif (not bit0 and not ir1(10) and bit1) = '1' then
bor_adr := ir1(3 downto 0);
br <= bor(to_integer(unsigned(bor_adr)));
currentState <= a10;
else
bor_adr := ir1(3 downto 0);
ir2 <= bor(to_integer(unsigned(bor_adr)));
currentState <= a4;
end if;
end case;
end proc_Funcmi;
begin
if (rst = '1') then
br <= (others => '0');
ext_in <= (others => '0');
idle <= '0';
inpr <= (others => '0');
ir1 <= (others => '0');
ir2 <= (others => '0');
pc <= (others => '0');
ralu <= (others => '0');
rialu <= (others => '0');
currentState <= a1;
idle <= '1';
elsif (clk'event and clk = '1') then
idle <= '0';
proc_Funcmi;
end if;
end process;
end ARC_Funcmi;
Books | ALBI_Books (Back to Top) | Fig_32
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package MY_PACKAGE is
procedure wave_gen (signal clk: out std_logic);
procedure exec_inst(signal idle : in std_logic; signal clk : out std_logic);
procedure alub(
alu_in1 : in std_logic_vector(15 downto 0); -- operand 1
alu_in2 : in std_logic_vector(15 downto 0); -- operand 2
alu_ctr : in std_logic_vector(4 downto 0); -- instruction alu_ctr
alu : out std_logic_vector(15 downto 0) -- alu out
);
procedure ialub(
ialu_in1 : in std_logic_vector(15 downto 0); -- operand 1
ialu_in2 : in std_logic_vector(15 downto 0); -- operand 2
ialu : out std_logic_vector(15 downto 0) -- output
);
end MY_PACKAGE;
package body MY_PACKAGE is
procedure wave_gen (signal clk: out std_logic) is
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end wave_gen;
procedure exec_inst(signal idle : in std_logic; signal clk : out std_logic) is
begin
wave_gen(clk);
while idle = '0' loop
wave_gen(clk);
end loop;
end exec_inst;
procedure alub(
alu_in1 : in std_logic_vector(15 downto 0); -- operand 1
alu_in2 : in std_logic_vector(15 downto 0); -- operand 2
alu_ctr : in std_logic_vector(4 downto 0); -- instruction alu_ctr
alu : out std_logic_vector(15 downto 0) -- alu out
) is
constant add : std_logic_vector (4 downto 0) := "00001";
constant log_and : std_logic_vector (4 downto 0) := "00010";
constant sub : std_logic_vector (4 downto 0) := "00011";
constant shl : std_logic_vector (4 downto 0) := "00100";
constant shr : std_logic_vector (4 downto 0) := "00101";
constant inc : std_logic_vector (4 downto 0) := "10010";
constant com : std_logic_vector (4 downto 0) := "10100";
variable valu_in1, valu_in2 : signed (15 downto 0);
variable vout : signed (15 downto 0);
begin
-- process
valu_in1 := signed (alu_in1);
valu_in2 := signed (alu_in2);
vout := x"0000";
case alu_ctr is
when add => -------------- add signed-----------------
vout := valu_in1 + valu_in2;
when sub => ------------ sub signed---------
vout := valu_in1 - valu_in2;
when log_and =>-------------- logic and ------
vout := valu_in1 and valu_in2;
when shl =>-------------- shift left ---------
vout := valu_in2 (14 downto 0) & '0';
when shr => -------------- shift right --------
vout := '0' & valu_in2 (15 downto 1);
when inc => ------------ increment -------------
vout := valu_in1 + 1;
when com => ----------- complement -------------
vout := not valu_in1;
when others => null; ------- others for case
end case;
-- assign alu_out signals
alu := std_logic_vector(vout);
end alub;
procedure ialub(
ialu_in1 : in std_logic_vector(15 downto 0); -- operand 1
ialu_in2 : in std_logic_vector(15 downto 0); -- operand 2
ialu : out std_logic_vector(15 downto 0) -- output
) is
begin
ialu := std_logic_vector(unsigned(ialu_in1) + unsigned(ialu_in2));
end ialub;
end MY_PACKAGE;
Books | ALBI_Books (Back to Top) | Fig_33
#include "Funcmi.h"
void Funcmi::main_proc()
{
if (rst.read() == 1)
{
br.write(0);
ext_in.write(0);
idle.write(0);
inpr.write(0);
ir1.write(0);
ir2.write(0);
pc.write(0);
ralu.write(0);
rialu.write(0);
for (unsigned int i = 0; i < 16; ++i)
{
bor[i].write(0);
}
for (unsigned int i = 0; i < 65536; ++i)
{
m0[i].write(0);
}
for (unsigned int i = 0; i < 65536; ++i)
{
m1[i].write(0);
}
currentState = a1;
idle.write(1);
}
else
{
idle.write(0);
proc_Funcmi();
}
}
void Funcmi::proc_Funcmi()
{
sc_uint<16> ir1_tmp = ir1.read();
ext_in.write(0);
idle.write(0);
switch (currentState)
{
case a1:
if (s.read() && dma.read() && ext_rdwr.read() && m.read())
{
m1_adr = ext_adr.read();
currentState = a1;
m1[m1_adr].write(ext_out.read());
idle.write(1);
}
else if (s.read() && dma.read() && ext_rdwr.read() && !m.read())
{
m0_adr = ext_adr.read();
currentState = a1;
m0[m0_adr].write(ext_out.read());
idle.write(1);
}
else if (s.read() && dma.read() && !ext_rdwr.read() && m.read())
{
m1_adr = ext_adr.read();
currentState = a1;
ext_in.write(m1[m1_adr].read());
idle.write(1);
}
else if (s.read() && dma.read() && !ext_rdwr.read() && !m.read())
{
m0_adr = ext_adr.read();
currentState = a1;
ext_in.write(m0[m0_adr].read());
idle.write(1);
}
else if (s.read() && !dma.read())
{
m0_adr = pc.read();
currentState = a8;
ir1.write(m0[m0_adr].read());
}
else
{
currentState = a1;
idle.write(1);
}
break;
case a2:
if (bit1.read())
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a1;
bor[bor_adr].write(br.read());
idle.write(1);
}
else
{
currentState = a6;
ir2.write(br.read());
}
break;
case a3:
{
alu_in1 = br.read();
alu_in2 = ir2.read();
alu_ctr = ir1_tmp.range(15, 11);
currentState = a5;
alub(alu_in1, alu_in2, alu_ctr, alu);
ralu.write(alu);
}
break;
case a4:
if (ir1_tmp[9])
{
m1_adr = ir2.read();
currentState = a2;
br.write(m1[m1_adr].read());
}
else
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a3;
br.write(bor[bor_adr].read());
}
break;
case a5:
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a1;
bor[bor_adr].write(ralu.read());
idle.write(1);
}
break;
case a6:
if (bit1.read())
{
m1_adr = ir2.read();
currentState = a2;
br.write(m1[m1_adr].read());
}
else
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a3;
br.write(bor[bor_adr].read());
}
break;
case a7:
{
currentState = a17;
pc.write(pc.read()+1);
}
break;
case a8:
{
currentState = a18;
pc.write(pc.read()+1);
}
break;
case a9:
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a1;
bor[bor_adr].write(inpr.read());
idle.write(1);
}
break;
case a10:
if (ir1_tmp[9])
{
currentState = a6;
ir2.write(br.read());
}
else
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a1;
bor[bor_adr].write(br.read());
idle.write(1);
}
break;
case a11:
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a1;
bor[bor_adr].write(br.read());
idle.write(1);
}
break;
case a12:
{
ialu_in1 = ir2.read();
ialu_in2 = br.read();
currentState = a15;
ialub(ialu_in1, ialu_in2, ialu);
rialu.write(ialu);
}
break;
case a13:
{
currentState = a16;
ir2.write(br.read());
}
break;
case a14:
if (bit0.read())
{
m1_adr = ir2.read();
currentState = a1;
pc.write(m1[m1_adr].read());
idle.write(1);
}
else
{
m1_adr = ir2.read();
currentState = a2;
br.write(m1[m1_adr].read());
}
break;
case a15:
{
currentState = a14;
ir2.write(rialu.read());
}
break;
case a16:
if (bit0.read() && ir1_tmp.range(3, 0) == "0000")
{
m1_adr = ir2.read();
currentState = a1;
pc.write(m1[m1_adr].read());
idle.write(1);
}
else if (!bit0.read() && ir1_tmp.range(3, 0) == "0000")
{
m1_adr = ir2.read();
currentState = a2;
br.write(m1[m1_adr].read());
}
else
{
bor_adr = ir1_tmp.range(3, 0);
currentState = a12;
br.write(bor[bor_adr].read());
}
break;
case a17:
if (ir1_tmp[8] && bit0.read())
{
currentState = a1;
pc.write(ir2.read());
idle.write(1);
}
else if (ir1_tmp[8] && !bit0.read() && bit1.read())
{
currentState = a11;
br.write(ir2.read());
}
else if (ir1_tmp[8] && !bit0.read() && !bit1.read())
{
bor_adr = ir1_tmp.range(7, 4);
currentState = a3;
br.write(bor[bor_adr].read());
}
else if (!ir1_tmp[8] && ir1_tmp[9])
{
m1_adr = ir2.read();
currentState = a13;
br.write(m1[m1_adr].read());
}
else if (!ir1_tmp[8] && !ir1_tmp[9] && bit0.read() && ir1_tmp.range(3, 0) == "0000")
{
m1_adr = ir2.read();
currentState = a1;
pc.write(m1[m1_adr].read());
idle.write(1);
}
else if (!ir1_tmp[8] && !ir1_tmp[9] && !bit0.read() && ir1_tmp.range(3, 0) == "0000")
{
m1_adr = ir2.read();
currentState = a2;
br.write(m1[m1_adr].read());
}
else
{
bor_adr = ir1_tmp.range(3, 0);
currentState = a12;
br.write(bor[bor_adr].read());
}
break;
case a18:
if (bit0.read() && bit1.read())
{
currentState = a9;
inpr.write(data_in.read());
}
else if (bit0.read() && !bit1.read() && ir1_tmp[10])
{
m0_adr = pc.read();
currentState = a7;
ir2.write(m0[m0_adr].read());
}
else if (bit0.read() && !bit1.read() && !ir1_tmp[10])
{
bor_adr = ir1_tmp.range(3, 0);
currentState = a1;
pc.write(bor[bor_adr].read());
idle.write(1);
}
else if (!bit0.read() && ir1_tmp[10])
{
m0_adr = pc.read();
currentState = a7;
ir2.write(m0[m0_adr].read());
}
else if (!bit0.read() && !ir1_tmp[10] && bit1.read())
{
bor_adr = ir1_tmp.range(3, 0);
currentState = a10;
br.write(bor[bor_adr].read());
}
else
{
bor_adr = ir1_tmp.range(3, 0);
currentState = a4;
ir2.write(bor[bor_adr].read());
}
break;
}
}
#ifdef MTI_SYSTEMC
SC_MODULE_EXPORT(Funcmi);
#endif
Books | ALBI_Books (Back to Top) | Fig_34
#include <iostream>
#include "systemc.h"
#include "ialu.h"
#include "alu.h"
SC_MODULE(Funcmi)
{
enum States { a1 = 1, a2, a3, a4, a5, a6, a7,
a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18 };
sc_signal< int > currentIf;
sc_signal< sc_uint<16> > bor[16];
sc_signal< sc_uint<16> > br;
sc_signal< sc_uint<16> > inpr;
sc_signal< sc_uint<16> > ir1;
sc_signal< sc_uint<16> > ir2;
sc_signal< sc_uint<16> > m0[65536];
sc_signal< sc_uint<16> > m1[65536];
sc_signal< sc_uint<16> > pc;
sc_signal< sc_uint<16> > ralu;
sc_signal< sc_uint<16> > rialu;
sc_in< bool > bit0;
sc_in< bool > bit1;
sc_in< sc_uint<16> > data_in;
sc_in< bool > dma;
sc_in< sc_uint<16> > ext_adr;
sc_in< sc_uint<16> > ext_out;
sc_in< bool > ext_rdwr;
sc_in< bool > m;
sc_in< bool > rst;
sc_in< bool > s;
sc_out< sc_uint<16> > ext_in;
sc_out< bool > idle;
sc_uint<4> bor_adr;
FSMStates currentState;
sc_uint<16> m0_adr;
sc_uint<16> m1_adr;
sc_in_clk clk;
void main_proc();
void proc_Funcmi();
SC_CTOR(Funcmi)
:
bit0 ("bit0"),
bit1 ("bit1"),
clk ("clk"),
data_in ("data_in"),
dma ("dma"),
ext_adr ("ext_adr"),
ext_in ("ext_in"),
ext_out ("ext_out"),
ext_rdwr ("ext_rdwr"),
idle ("idle"),
m ("m"),
rst ("rst"),
s ("s")
{
SC_METHOD(main_proc);
sensitive << clk.pos() << rst;
}
};
Books | ALBI_Books (Back to Top) | Fig_031
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.components.all;
entity Structm is
port (
bit0 : in std_logic;
bit1 : in std_logic;
bor_en : out std_logic;
br_en : out std_logic;
clk : in std_logic;
comp4_1_dout : in std_logic;
ctr_mux0 : out std_logic;
ctr_mux1_0 : out std_logic;
ctr_mux1_1 : out std_logic;
ctr_mux1_2 : out std_logic;
ctr_mux2_0 : out std_logic;
ctr_mux2_1 : out std_logic;
ctr_mux2_2 : out std_logic;
dma : in std_logic;
ext_rdwr : in std_logic;
idle : out std_logic;
inpr_en : out std_logic;
ir1_10 : in std_logic;
ir1_8 : in std_logic;
ir1_9 : in std_logic;
ir1_en : out std_logic;
ir2_en : out std_logic;
m : in std_logic;
m0_rdwr : out std_logic;
m1_rdwr : out std_logic;
pc_count : out std_logic;
pc_en : out std_logic;
ralu_en : out std_logic;
rialu_en : out std_logic;
rst : in std_logic;
s : in std_logic
);
end Structm;
architecture ARC_Structm of Structm is
type FSMStates is (
a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15,
a16, a17, a18
);
signal currentState : FSMStates;
begin
process (clk , rst)
procedure proc_Structm is
begin
bor_en <= '0';
br_en <= '0';
ctr_mux0 <= '0';
ctr_mux1_0 <= '0';
ctr_mux1_1 <= '0';
ctr_mux1_2 <= '0';
ctr_mux2_0 <= '0';
ctr_mux2_1 <= '0';
ctr_mux2_2 <= '0';
idle <= '0';
inpr_en <= '0';
ir1_en <= '0';
ir2_en <= '0';
m0_rdwr <= '0';
m1_rdwr <= '0';
pc_count <= '0';
pc_en <= '0';
ralu_en <= '0';
rialu_en <= '0';
case currentState is
when a1 =>
if (s and dma and ext_rdwr and m) = '1' then
m1_rdwr <= '1';
currentState <= a1;
idle <= '1';
elsif (s and dma and ext_rdwr and not m) = '1' then
m0_rdwr <= '1';
currentState <= a1;
idle <= '1';
elsif (s and dma and not ext_rdwr and m) = '1' then
ctr_mux2_0 <= '1';
currentState <= a1;
idle <= '1';
elsif (s and dma and not ext_rdwr and not m) = '1' then
ctr_mux2_2 <= '1';
currentState <= a1;
idle <= '1';
elsif (s and not dma) = '1' then
ctr_mux1_1 <= '1';
ir1_en <= '1';
currentState <= a2;
else
currentState <= a1;
idle <= '1';
end if;
when a2 =>
pc_count <= '1';
currentState <= a3;
when a3 =>
if (bit0 and bit1) = '1' then
inpr_en <= '1';
currentState <= a4;
elsif (bit0 and not bit1 and ir1_10) = '1' then
ir2_en <= '1';
ctr_mux1_1 <= '1';
ctr_mux2_2 <= '1';
currentState <= a5;
elsif (bit0 and not bit1 and not ir1_10) = '1' then
pc_en <= '1';
currentState <= a1;
idle <= '1';
elsif (not bit0 and ir1_10) = '1' then
ir2_en <= '1';
ctr_mux1_1 <= '1';
ctr_mux2_2 <= '1';
currentState <= a5;
elsif (not bit0 and not ir1_10 and bit1) = '1' then
br_en <= '1';
currentState <= a7;
else
ir2_en <= '1';
currentState <= a8;
end if;
when a4 =>
ctr_mux1_0 <= '1';
ctr_mux0 <= '1';
bor_en <= '1';
ctr_mux1_1 <= '1';
currentState <= a1;
idle <= '1';
when a5 =>
pc_count <= '1';
currentState <= a6;
when a6 =>
if (ir1_8 and bit0) = '1' then
ctr_mux2_1 <= '1';
pc_en <= '1';
currentState <= a1;
idle <= '1';
elsif (ir1_8 and not bit0 and bit1) = '1' then
br_en <= '1';
ctr_mux2_1 <= '1';
currentState <= a14;
elsif (ir1_8 and not bit0 and not bit1) = '1' then
br_en <= '1';
ctr_mux0 <= '1';
currentState <= a11;
elsif (not ir1_8 and ir1_9) = '1' then
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a12;
elsif (not ir1_8 and not ir1_9 and comp4_1_dout and bit0) = '1' then
ctr_mux2_0 <= '1';
ctr_mux1_0 <= '1';
pc_en <= '1';
currentState <= a1;
idle <= '1';
elsif (not ir1_8 and not ir1_9 and comp4_1_dout and not bit0) = '1' then
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a10;
else
br_en <= '1';
currentState <= a16;
end if;
when a7 =>
if (ir1_9) = '1' then
ctr_mux2_0 <= '1';
ir2_en <= '1';
ctr_mux2_1 <= '1';
currentState <= a9;
else
ctr_mux0 <= '1';
ctr_mux1_2 <= '1';
bor_en <= '1';
currentState <= a1;
idle <= '1';
end if;
when a8 =>
if (ir1_9) = '1' then
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a10;
else
br_en <= '1';
ctr_mux0 <= '1';
currentState <= a11;
end if;
when a9 =>
if (bit1) = '1' then
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a10;
else
br_en <= '1';
ctr_mux0 <= '1';
currentState <= a11;
end if;
when a10 =>
if (bit1) = '1' then
ctr_mux0 <= '1';
ctr_mux1_2 <= '1';
bor_en <= '1';
currentState <= a1;
idle <= '1';
else
ctr_mux2_0 <= '1';
ir2_en <= '1';
ctr_mux2_1 <= '1';
currentState <= a9;
end if;
when a11 =>
ralu_en <= '1';
currentState <= a13;
when a12 =>
ctr_mux2_0 <= '1';
ir2_en <= '1';
ctr_mux2_1 <= '1';
currentState <= a15;
when a13 =>
ctr_mux1_0 <= '1';
ctr_mux0 <= '1';
ctr_mux1_2 <= '1';
bor_en <= '1';
currentState <= a1;
idle <= '1';
when a14 =>
ctr_mux0 <= '1';
ctr_mux1_2 <= '1';
bor_en <= '1';
currentState <= a1;
idle <= '1';
when a15 =>
if (comp4_1_dout and bit0) = '1' then
ctr_mux2_0 <= '1';
ctr_mux1_0 <= '1';
pc_en <= '1';
currentState <= a1;
idle <= '1';
elsif (comp4_1_dout and not bit0) = '1' then
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a10;
else
br_en <= '1';
currentState <= a16;
end if;
when a16 =>
rialu_en <= '1';
currentState <= a17;
when a17 =>
ctr_mux2_0 <= '1';
ir2_en <= '1';
ctr_mux2_2 <= '1';
currentState <= a18;
when a18 =>
if (bit0) = '1' then
ctr_mux2_0 <= '1';
ctr_mux1_0 <= '1';
pc_en <= '1';
currentState <= a1;
idle <= '1';
else
ctr_mux2_0 <= '1';
br_en <= '1';
ctr_mux1_0 <= '1';
currentState <= a10;
end if;
end case;
end proc_Structm;
begin
if (rst = '1') then
bor_en <= '0';
br_en <= '0';
ctr_mux0 <= '0';
ctr_mux1_0 <= '0';
ctr_mux1_1 <= '0';
ctr_mux1_2 <= '0';
ctr_mux2_0 <= '0';
ctr_mux2_1 <= '0';
ctr_mux2_2 <= '0';
idle <= '0';
inpr_en <= '0';
ir1_en <= '0';
ir2_en <= '0';
m0_rdwr <= '0';
m1_rdwr <= '0';
pc_count <= '0';
pc_en <= '0';
ralu_en <= '0';
rialu_en <= '0';
currentState <= a1;
idle <= '1';
elsif (clk'event and clk = '0') then
idle <= '0';
proc_Structm;
end if;
end process;
end ARC_Structm;
Books | ALBI_Books (Back to Top) | Fig_034
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------
entity top is
port
(
bit0 : in std_logic;
bit1 : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dma : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_in : out std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(15 downto 0);
ext_rdwr : in std_logic;
idle : out std_logic;
m : in std_logic;
rst : in std_logic;
s : in std_logic
);
end top;
-----------------------------------------------
architecture arc_top of top is
component Structm is
port (
bit0 : in std_logic;
bit1 : in std_logic;
bor_en : out std_logic;
br_en : out std_logic;
clk : in std_logic;
comp4_1_dout : in std_logic;
ctr_mux0 : out std_logic;
ctr_mux1_0 : out std_logic;
ctr_mux1_1 : out std_logic;
ctr_mux1_2 : out std_logic;
ctr_mux2_0 : out std_logic;
ctr_mux2_1 : out std_logic;
ctr_mux2_2 : out std_logic;
dma : in std_logic;
ext_rdwr : in std_logic;
idle : out std_logic;
inpr_en : out std_logic;
ir1_10 : in std_logic;
ir1_8 : in std_logic;
ir1_9 : in std_logic;
ir1_en : out std_logic;
ir2_en : out std_logic;
m : in std_logic;
m0_rdwr : out std_logic;
m1_rdwr : out std_logic;
pc_count : out std_logic;
pc_en : out std_logic;
ralu_en : out std_logic;
rialu_en : out std_logic;
rst : in std_logic;
s : in std_logic
);
end component;
component dp is
port
(
-- Inputs from control unit
ctr_mux2_0 : in std_logic; --(y1)
br_en : in std_logic; --(y2)
ctr_mux1_0 : in std_logic; --(y3)
ctr_mux0 : in std_logic; --(y4)
ir2_en : in std_logic; --(y5)
ctr_mux1_2 : in std_logic; --(y6)
bor_en : in std_logic; --(y7)
ralu_en : in std_logic; --(y8)
ctr_mux2_1 : in std_logic; --(y9)
pc_en : in std_logic; --(y10)
inpr_en : in std_logic; --(y11)
ctr_mux1_1 : in std_logic; --(y12)
m1_rdwr : in std_logic; --(y13)
m0_rdwr : in std_logic; --(y14)
ctr_mux2_2 : in std_logic; --(y15)
rialu_en : in std_logic; --(y16)
pc_count : in std_logic; --(y17)
ir1_en : in std_logic; --(y18)
-- Inputs from outside
clk : in std_logic;
rst : in std_logic;
ext_adr : in std_logic_vector(15 downto 0);
ext_out : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
-- Outputs to control unit
ir1_9 : out std_logic; --(x1)
ir1_10 : out std_logic; --(x2)
ir1_8 : out std_logic; --(x3)
comp4_1_dout : out std_logic; --(x10)
-- Outputs to outside
ext_in : out std_logic_vector(15 downto 0)
);
end component;
-- output of control unit
signal ctr_mux2_0 : std_logic;
signal br_en : std_logic;
signal ctr_mux1_0 : std_logic;
signal ctr_mux0 : std_logic;
signal ir2_en : std_logic;
signal ctr_mux1_2 : std_logic;
signal bor_en : std_logic;
signal ralu_en : std_logic;
signal ctr_mux2_1 : std_logic;
signal pc_en : std_logic;
signal inpr_en : std_logic;
signal ctr_mux1_1 : std_logic;
signal m1_rdwr : std_logic;
signal m0_rdwr : std_logic;
signal ctr_mux2_2 : std_logic;
signal rialu_en : std_logic;
signal pc_count : std_logic;
signal ir1_en : std_logic;
-- output of operational unit
signal ir1_9 : std_logic;
signal ir1_10 : std_logic;
signal ir1_8 : std_logic;
signal comp4_1_dout : std_logic;
begin
u1_fsm : structm port map
(
bit0 => bit0 ,
bit1 => bit1 ,
bor_en => bor_en ,
br_en => br_en ,
clk => clk ,
comp4_1_dout => comp4_1_dout ,
ctr_mux0 => ctr_mux0 ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux1_1 => ctr_mux1_1 ,
ctr_mux1_2 => ctr_mux1_2 ,
ctr_mux2_0 => ctr_mux2_0 ,
ctr_mux2_1 => ctr_mux2_1 ,
ctr_mux2_2 => ctr_mux2_2 ,
dma => dma ,
ext_rdwr => ext_rdwr ,
idle => idle ,
inpr_en => inpr_en ,
ir1_10 => ir1_10 ,
ir1_8 => ir1_8 ,
ir1_9 => ir1_9 ,
ir1_en => ir1_en ,
ir2_en => ir2_en ,
m => m ,
m0_rdwr => m0_rdwr ,
m1_rdwr => m1_rdwr ,
pc_count => pc_count ,
pc_en => pc_en ,
ralu_en => ralu_en ,
rialu_en => rialu_en ,
rst => rst ,
s => s
);
u2_dp : dp port map
(
clk => clk ,
rst => rst ,
ext_adr => ext_adr ,
ext_out => ext_out ,
data_in => data_in ,
ctr_mux2_0 => ctr_mux2_0 ,
br_en => br_en ,
ctr_mux1_0 => ctr_mux1_0 ,
ctr_mux0 => ctr_mux0 ,
ir2_en => ir2_en ,
ctr_mux1_2 => ctr_mux1_2 ,
bor_en => bor_en ,
ralu_en => ralu_en ,
ctr_mux2_1 => ctr_mux2_1 ,
pc_en => pc_en ,
inpr_en => inpr_en ,
ctr_mux1_1 => ctr_mux1_1 ,
m1_rdwr => m1_rdwr ,
m0_rdwr => m0_rdwr ,
ctr_mux2_2 => ctr_mux2_2 ,
rialu_en => rialu_en ,
pc_count => pc_count ,
ir1_en => ir1_en ,
ext_in => ext_in ,
ir1_9 => ir1_9 ,
ir1_10 => ir1_10 ,
ir1_8 => ir1_8 ,
comp4_1_dout => comp4_1_dout
);
end arc_top;
-----------------------------------
configuration cfg_top of top is
for arc_top
end for;
end cfg_top;
------------------------------------
Books | ALBI_Books (Back to Top) | ALBI.zip
ALBI