Design your chips with Synthagate
Samary Baranov, CEO of Synthezza
The electronic industry needs High Level Synthesis tools. Why? The tremendous achievements in chip technology allow the production of chips with billions of gates. At the same time, the design technology of these circuits has only slightly improved in the last ten years, especially at the highest system level. The traditional digital system design flow contains the manual creation of a system description at RTL (Register Transfer Level) with Verilog or VHDL code. As a result, the time-to-market is increased three to four times for complex SoCs (Systems-on-Chip). The only way to reduce the gap between the future technological capability and the lagging designer productivity is to raise the design from the current RTL to the algorithmic or behavior level and to develop High level synthesis (HLS) tools.
State of the art. In the last ten years, several companies such as Cadence, Xilinx (bought by AMD on Oct. 27, 2020), Altera (bought by Intel on Dec. 28, 2015), Mentor Graphics (bought by Siemens, Nov. 14, 2016), and Forte Design Systems (bought by Cadence on Feb. 17, 2014), produced several HLS tools. However, according to analysts in the Electronic Design Automation (EDA) industry, all these tools present the third generation of HLS tools oriented to the design of a very restricted class of digital systems (Data Path dominated). These analysts predict that the fourth generation of HLS tools for the design of any digital system (Data Path and Control dominated) will appear only in several years.
HLS and RTL tool Synthagate. Synthagate is the tool for the design of Control and Data Path intensive systems with very complex Control Units containing numerous inputs and outputs. It performs full automatic synthesis of digital systems from behavior specification to HDL description at the Register Transfer Level (RTL). Synthagate allows to quickly implement, check, and estimate multiple design versions; to find an optimized solution for the design problems; to produce design documentation automatically; and to simplify the digital system verification problems. Synthagate is the first true 4th generation HLS tool that shortens the time-to-market by a factor of 3-4 for complex System-on-Chip (SoC) designs. The main difference between Synthagate and other design tools is that the designer isn’t required to use hardware description languages.
Applications. Synthagate covers most digital systems designs from DSP to Processing Units. It can be used in the design of robots, controllers, processors, IoT and AI systems, digital systems for automated and autonomous cars, etc. Besides, Synthagate can also be useful for students and educators of universities and colleges in courses such as Digital system design, Systems on the chips, VLSI system design, Embedded systems, Computer system architecture, and many others.
Our Solutions. Synthagate was developed with the primary focus of helping its users to develop complex digital systems. Here are the solutions that Synthagate provides:
The designer is not required to use hardware description languages. At the initial stage of the design, the designer describes the designed system's behavior with Algorithmic state machines.
In only two to three days, the designer can begin to use Synthagate to describe design system behaviors at a high level of representation. Most importantly, not only experienced hardware designers, but application engineers can design complex digital systems with Synthagate.
The designer is not required to think about the optimization of the initial description. Synthagate implements that automatically.
The designer presents the behavior of the designed system with a set of very simple ASMs. All other work is with ASM transformations (the ASM combining, the ASM minimization, the insertion of subASMs, ASMs equivalence check, etc.) Synthagate implements this automatically using very effective optimizing algorithms.
Using different subASMs, a designer can quickly design and check different architectures by time and/or area.
The designer can immediately use any preliminary designed IP cores, including designs from other companies.
The designer is not required to think about the design and optimization of buses. Synthagate automatically creates direct and indirect connections (buses) between units using procedures that optimize not only the Data path (its area and speed) but also the Control unit constructed at the following design stages.
Synthagate provides the designer with a simple and easy-to-use graphic interface.
In case of design errors, the designer can identify them not on VHDL or Verilog, but on the Algorithmic state machine level. It reduces the search and correction of mistakes by several times.
In the process of design, Synthagate creates documents corresponding to each design stage. These documents can be used to prepare project documentation. In the case of designer errors at the initial stages of the project, these documents allow the designer to quickly return to previous design stages and fix all possible problems.
Logic synthesis of Synthagate reduces the circuit area for combinational circuits and Finite State Machines on the chip by as much as 20% - 50%, compared with results of the best USA industrial tools from Synopsys, Xilinx, Altera, and Mentor Graphics. The run time of these tools exceed that of Synthagate by more than a factor of 5.
In most SoCs, a Control unit is an irregular multi-level and multi-output circuit in which a delay of connectors between gates may be a lot more than a delay of gates themselves. Synthagate can construct optimized six-matrix regular FSM's circuits while minimizing the area and increasing the speed. It is especially important for SoCs.
Our Demos. Synthezza has developed a series of video demonstrations for the Synthagate tool titled, "From Algorithm to Digital System". Each video in the demo series has an extended PDF transcript and downloadable examples to try with Synthagate. Everything you need can be found in the video descriptions.
If you want to see an unusual project, you can find the design SuperNonsenseAltera in Demo 2: Complex HLS & RTL Designs. In this project, we wanted to test the possibility of the automatic design of very complex digital systems. For that, we gathered very different modes (operations) from various projects – robots, controllers, processors, communication devices, and games in one heap. The folder SuperNonsenseAltera and the folders constructed during this design are all available for download at www.synthezza.com/105-examples.
Judging by the reviews, the most significant interest among our videos was indicated by Demo 3. This video demonstrates the design of 105 projects in real-time under seven and a half minutes. Yes, you read that, right! And at the beginning, we only had Algorithmic State Machines and nothing else. There was no VHDL, no Verilog, or anything else.
You can get more information from Prof. Samary Baranov's latest books available on Amazon in ebook and paperback.
The beta version of Synthagate can be downloaded for a two month free trial here.