Demo 3: 105 HLS & RTL Design in 8 Minutes

Updated: Jul 1


Download Demo 3 Extended Transcript.pdf


Demo 3 Overview


In this video, we will demonstrate the design of 105 projects in real-time with our tool Synthagate, а product of Synthezza company. Don't worry. We will do this in under seven and a half minutes. I will also explain how I chose the examples for this 105-design marathon.


In this demo, we have three sets of projects:

  • GUI – beginning from ASMs, constructed with ASM Creator.

  • CPP – beginning from ASMs in System C.

  • VHD – beginning from ASMs in VHDL.

After the design, we’ll have 38,511 files in 2,126 folders. And at the beginning, we only had Algorithmic State Machines, and nothing else. There was no VHDL, no Verilog or anything else.



Demo 3 Examples


To download the examples, please login/sign-up to access 105 HLS & RTL Designs.


To read the introduction to the demo video series, visit Demo Series Intro. To download ASM creator, visit ASM Creator.



Note: Unfortunately, we are about two weeks away from launching the beta version of Synthagate due to technical reasons. You will be able to download and try it for free in mid-July. If you have any ideas, suggestions or comments we would be delighted to hear from you at info@synthezza.com. Please subscribe below to be the first to get notified of new presentations and course details.


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PRODUCTS

Synthagate—HLS & RTL

     Synthagate Overview

     What makes Synthagate different

     Examples of High Level and RTL Design

          Synthesis From GUI

          Synthesis From SystemC

          Synthesis From VHDL

Logic Synthesizer

     Overview
     Logic Synthesizer Experiments

     Benchmarks

DESIGN TECHNOLOGY

Algorithmic State machines in HLS

     What is Algorithmic State Machine?

     Time in ASM

     ASM in GUI, System C and VHDL

     ASM Transformations

          Asm Combining

          Asm Minimization

          SubAsm Inclusion

High Level Synthesis

     How Does Synthagate Work

     ASM Creator Short Manual

Synthesis at Register Transfer Level (RTL)

     Data Path

     Control Unit

     Top Design

BOOKS

  

DEMO SERIES

  

COMPANY

     About Us

     Contact US

  

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