Demo 3: 105 HLS & RTL Design in 8 Minutes
Updated: Jul 15, 2020
Download Demo 3 Extended Transcript.pdf
Demo 3 Overview
In this video, we will demonstrate the design of 105 projects in real-time with our tool Synthagate, а product of Synthezza company. Don't worry. We will do this in under seven and a half minutes. I will also explain how I chose the examples for this 105-design marathon.
In this demo, we have three sets of projects:
GUI – beginning from ASMs, constructed with ASM Creator.
CPP – beginning from ASMs in System C.
VHD – beginning from ASMs in VHDL.
After the design, we’ll have 38,511 files in 2,126 folders. And at the beginning, we only had Algorithmic State Machines, and nothing else. There was no VHDL, no Verilog or anything else.
Demo 3 Examples
To download the examples, please login/sign-up to access 105 HLS & RTL Designs.
To read the introduction to the demo video series, visit Demo Series Intro. To download ASM creator, visit ASM Creator.
Note: Unfortunately, we are about two weeks away from launching the beta version of Synthagate due to technical reasons. You will be able to download and try it for free in mid-July. If you have any ideas, suggestions or comments we would be delighted to hear from you at firstname.lastname@example.org. Please subscribe below to be the first to get notified of new presentations and course details.