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Introduction to the Demo Video Series

Updated: Aug 10

I would like to introduce you to a series of video presentations called From an Algorithm to a Digital System Design, on High level and RTL design using the new version of tool Synthagate, a product of Synthezza.


I am planning to share with you at least a dozen designs in the next few months accompanied with extended commentary and detailed descriptions beginning from external specifications to High level synthesis (HLS) and Register transfer level (RTL). You will get access to the most intermediate files obtained during design. You can find the first design here: Demo 1: Design Codec in under 5 seconds.


But first, a little history. For a long time, the main goal of my scientific research and technical applications were Algorithmic State Machines (ASMs) and Finite State Machines (FSMs). I can even boast a little that quite interesting results have been obtained, such as:​

  • Minimization of ASMs;

  • ASMs combining;

  • Check of ASM equivalence;

  • The decomposition of FSM with a lot of inputs and outputs which fundamentally different from the decomposition model of Hartmanis and Stearns;

  • ASM decomposition;

  • Synthesis of FSMs Mealy, Moore and their combined model from ASMs;

  • Synthesis of multilevel and multioutput logical circuits etc.


But of course, the upcoming presentations will not be about that. I understood that using ASMs you can very simply and efficiently describe the behavior of digital systems. Although, the entire time I had a nagging thought: why did I use ASMs only to design controllers or Control units of digital systems? For this reason, 15 years ago I started developing methods, algorithms and tools for the automatic design of digital systems whose behavior is represented by Algorithmic State Machines. When I understood that the method, algorithms and programs were almost ready, I decided to write a book about High level and Register transfer level synthesis of digital systems. However, by the time it was almost done, I realized that I no longer wanted to publish it. First, it was a very long book of almost 600 pages - which is not suitable for many readers. Who wants to read such a long book nowadays, even if it’s fiction? Second, I wanted to provide several case studies using HLS, which would make the book even longer. So, I decided to split the content into two books, and shorten them. As a result, Algorithmic State Machines and Finite state machines and High level synthesis of digital systems were published in Amazon in ebook and paperback versions in 2018. The books sell pretty well, with an average of 12 to 15 books per month. But what really disappointed me was that out of ten books sold, only three were about High Level. After all, I wanted to write a book about HLS and was even a little proud that it is one of the few books on this topic. My friends reassured me that most hardware developers are not yet ready for High level synthesis.


Are we not ready for HLS?


But I think this is not true. Obviously, I didn't demonstrate the excellent possibilities of using ASM in High level and Register transfer level design well enough. That is why I decided to give this set of presentation of HLS and RTL designs with Synthagate. The first of which is available to be seen right now.  You may wonder why I decided to show so many examples. Here is why: There are several HLS tools currently on the market developed by large companies such as Xilinx, Cadence, Siemens (Mentor Graphics inside Siemens), among several others. They use a subset of C or C++ to present the behavior of the designed system at the High level. From time to time, there have been reports from various sources that the tools mentioned above are Data path dominated. This means that these tools are good for designing systems with very complex blocks implementing non-trivial mathematical calculations, but instead with simple Control units. In fact, I don’t believe in it and I hope that the tools, constructed by leaders in the EDA industry, are good enough for designing a wide class of systems. However, I haven’t found a single example of a complex design made using these tools, besides filters and matrix processing systems. This is why I decided to give many non-trivial examples with detailed demonstration and descriptions of most of the steps of each design.


What's different in this tool?


The main difference between Synthagate and other design tools is that Synthagate uses Algorithmic State Machines (ASMs) at different design steps. It implements the design of Control and Data Path Intensive Systems with very complex Control Units containing numerous inputs and outputs. Synthagate covers most digital system designs from DSP to Processing Units. It can be used in design of robots, controllers, processors, IoT & AI systems, video and voice processing systems, digital systems for automated and autonomous cars etc. Besides, Synthagate can be effectively used in numerous university courses. But most importantly, by using Synthagate, not only hardware designers, but also application engineers will be able to design complex digital systems. Of course, these designers should get to know the design methodology implemented in Synthagate. To do this, I am planning to open a special online course very soon, so stay tuned. 

What you'll learn


Each demo-presentation will consist of a rather short video demonstration of the design with a more detailed script (downloadable pdf file) of the design process. I apologize in advance for my accent on the video, but please turn on your subtitles. My intention is to bring you short videos, but also give detailed explanations in the accompanied pdf files.  The beta version of Synthagate will be available on our site at the end of June. You will be able to download and try it for free. If you have any ideas, suggestions or comments we would be delighted to hear from you at info@synthezza.com. Please subscribe below to be the first to get notified of new presentations and course details. Thank you,  Prof. Samary Baranov



Demo 1 >

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PRODUCTS

Synthagate—HLS & RTL

     Synthagate Overview

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Logic Synthesizer

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HLS & RTL TECHNOLOGY

Algorithmic State machines in HLS

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     Time in ASM

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High Level Synthesis

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Synthesis at Register Transfer Level (RTL)

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ASM Creator Manual

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Benchmarks of High Level Synthesis

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105 Designs at High Level and RTL

Logic Designs

     FSMs

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